A novel approach to IC, package and board co-optimization

Today's leading edge IC (Integrated Circuit) packaging technologies require a co-design methodology that streamlines the planning, assembly, and optimization of the IC die, package substrate, and PCB (Printed Circuit Board) while assimilating the physical and logical interactions between each design domain. Package pin-outs and other packaging interconnect structures, such as bridges and interposers, must not only be optimized based on die level constraints, but also on the constraints, escape routing, and pin-outs of critical interfaces on the PCB. In short, the concept of throwing your design over the wall and letting the next guy deal with it, no longer works. This paper outlines a methodology for the concurrent design and optimization of IC dies, packages and PCBs.

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