A cross-layer adaptive approach for performance and power optimization in STT-MRAM

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising candidate as a universal on-chip memory technology due to non-volatility, high density and scalability. However, high write energy and latency are major challenges in this memory technology due to the asymmetry and stochastic nature of the write operation. Typically, the write current is set for the minimum energy point, which can further impact the write latency. To mitigate these issues, we propose an adaptive write current scaling technique that adjusts the write current, and hence the write latency and energy based on the performance needs at run-time. Using this technique, optimal energy and performance points for write current are obtained using detailed device and system level analysis. Furthermore, we use runtime adaptation of write current by predicting the write access rate for the next execution phase. We evaluate the efficiency of the proposed approach on SPEC2000 applications for STT-MRAM-based L1 and L2-cache levels. The results show that the effective write latency of L1 and L2 is reduced by 52.4% and 55.7% with 7.6% and 1.4% area overheads, respectively, corresponding to the overall system performance optimization of 15.5% while the total memory energy consumption is increasing by only 3.2%.

[1]  Somayeh Sardashti,et al.  The gem5 simulator , 2011, CARN.

[2]  Mehdi B. Tahoori,et al.  Improving Write Performance for STT-MRAM , 2016, IEEE Transactions on Magnetics.

[3]  Mehdi Baradaran Tahoori,et al.  Leveraging Systematic Unidirectional Error-Detecting Codes for fast STT-MRAM cache , 2017, 2017 IEEE 35th VLSI Test Symposium (VTS).

[4]  Cong Xu,et al.  NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  B. Dieny,et al.  A compact model of precessional spin-transfer switching for MTJ with a perpendicular polarizer , 2012, 2012 28th International Conference on Microelectronics Proceedings.

[6]  Sachin S. Sapatnekar,et al.  Improving STT-MRAM density through multibit error correction , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[7]  Swaroop Ghosh,et al.  Impact of process-variations in STTRAM and adaptive boosting for robustness , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[8]  Mehdi Baradaran Tahoori,et al.  Self-Timed Read and Write Operations in STT-MRAM , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Jun Yang,et al.  Energy reduction for STT-RAM using early write termination , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[10]  Kaushik Roy,et al.  AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Daisuke Suzuki,et al.  Cost-Efficient Self-Terminated Write Driver for Spin-Transfer-Torque RAM and Logic , 2014, IEEE Transactions on Magnetics.

[12]  Mircea R. Stan,et al.  Relaxing non-volatility for fast and energy-efficient STT-RAM caches , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[13]  Yu Cao,et al.  New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration , 2006, IEEE Transactions on Electron Devices.

[14]  Xueti Tang,et al.  Spin-transfer torque magnetic random access memory (STT-MRAM) , 2013, JETC.

[15]  Jaeyoung Park,et al.  Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring , 2013, International Symposium on Low Power Electronics and Design (ISLPED).

[16]  Mehdi Baradaran Tahoori,et al.  Avoiding unnecessary write operations in STT-MRAM for low power implementation , 2014, Fifteenth International Symposium on Quality Electronic Design.

[17]  Mehdi Baradaran Tahoori,et al.  Opportunistic write for fast and reliable STT-MRAM , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[18]  Wenqing Wu,et al.  Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[19]  Mircea R. Stan,et al.  The Promise of Nanomagnetics and Spintronics for Future Logic and Universal Memory , 2010, Proceedings of the IEEE.

[20]  Kiyoung Choi,et al.  DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture , 2014, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA).