A model for crosstalk noise evaluation in deep submicron processes

To certify, the correctness of a design, in deep submicron technologies, the verification process has to cover some new issues. The noise introduced on signals through the crosstalk coupling is one of these emerging problems. In this paper, we propose a model to evaluate the peak value of the noise injected on a signal during the transition of its neighboring signals. This model has been used in a prototype verification tool and has shown a satisfying accuracy within a reasonable computation delay.

[1]  Amjad Hajjar.  Modelisation des temps de propagation et analyse temporelle statique des circuits integres cmos , 1992 .

[2]  Dongsheng Wang,et al.  Post global routing crosstalk risk estimation and reduction , 1996, Proceedings of International Conference on Computer Aided Design.

[3]  Hai Zhou,et al.  An optimal algorithm for river routing with crosstalk constraints , 1996, Proceedings of International Conference on Computer Aided Design.

[4]  D. M. H. Walker,et al.  Timing analysis of combinational circuits including capacitive coupling and statistical process variation , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[5]  Bernard N. Sheehan.  Predicting coupled noise in RC circuits , 2000, DATE '00.

[6]  D. Overhauser,et al.  Full-chip verification of UDSM designs , 1998, ICCAD '98.

[7]  Hai Zhou,et al.  An optimal algorithm for river routing with crosstalk constraints , 1996, ICCAD 1996.

[8]  Kenneth L. Shepard,et al.  Noise in deep submicron digital design , 1996, Proceedings of International Conference on Computer Aided Design.

[9]  Alain Greiner,et al.  TAS: an accurate timing analyser for CMOS VLSI , 1991, Proceedings of the European Conference on Design Automation..