Hw/Sw Co-Design for Low Power Arithmetic and Logic Units
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[1] Kaushik Roy,et al. Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories , 2000, ISLPED '00.
[2] Thomas D. Burd,et al. Design issues for Dynamic Voltage Scaling , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).
[3] Mark C. Johnson,et al. Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks , 1998, ISLPED '98.
[4] Shekhar Y. Borkar,et al. Design challenges of technology scaling , 1999, IEEE Micro.
[5] K. Roy,et al. DRG-cache: a data retention gated-ground cache for low power , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).
[6] Krste Asanovic,et al. Banked multiported register files for high-frequency superscalar microprocessors , 2003, ISCA '03.
[7] Sang Lyul Min,et al. Dynamic voltage scaling algorithm for dynamic-priority hard real-time systems using slack time analysis , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[8] Michael S. Hsiao,et al. Compiler-directed dynamic voltage/frequency scheduling for energy reduction in microprocessors , 2001, ISLPED '01.