Dynamic Allocation/Reallocation of Dark Cores in Many-Core Systems for Improved System Performance

A significant number of processing cores in any many-core systems nowadays and likely in the future have to be switched off or forced to be idle to become dark cores, in light of ever increasing power density and chip temperature. Although these dark cores cannot make direct contributions to the chip’s throughput, they can still be allocated to applications currently running in the system for the sole purpose of heat dissipation enabled by the temperature gradient between the active and dark cores. However, allocating dark cores to applications tends to add extra waiting time to applications yet to be launched, which in return can have adverse implications on the overall system performance. Another big issue related to dark core allocation stems from the fact that application characteristics are prone to undergo rapid changes at runtime, making a fixed dark core allocation scheme less desirable. In this paper, a runtime dark core allocation and dynamic adjustment scheme is thus proposed. Built upon a dynamic programming network (DPN) framework, the proposed scheme attempts to optimize the performance of currently running applications and simultaneously reduce waiting times of incoming applications by taking into account both thermal issues and geometric shapes of regions formed by the active/dark cores. The experimental results show that the proposed approach achieves an average of 61% higher throughput than the two state-of-the-art thermal-aware runtime task mapping approaches, making it the runtime resource management of choice in many-core systems.

[1]  Muhammad Shafique,et al.  Defragmentation of Tasks in Many-Core Architecture , 2017, ACM Trans. Archit. Code Optim..

[2]  Bharadwaj Veeravalli,et al.  Reliability and Energy-Aware Mapping and Scheduling of Multimedia Applications on Multiprocessor Systems , 2016, IEEE Transactions on Parallel and Distributed Systems.

[3]  Bharadwaj Veeravalli,et al.  Communication and migration energy aware task mapping for reliable multiprocessor systems , 2014, Future Gener. Comput. Syst..

[4]  Hamid Sarbazi-Azad,et al.  Efficient processor allocation in a reconfigurable CMP architecture for dark silicon era , 2016, 2016 IEEE 34th International Conference on Computer Design (ICCD).

[5]  Yuhua Tang,et al.  Reducing Static Energy in Supercomputer Interconnection Networks Using Topology-Aware Partitioning , 2016, IEEE Transactions on Computers.

[6]  Xiaohang Wang,et al.  On runtime adaptive tile defragmentation for resource management in many-core systems , 2016, Microprocess. Microsystems.

[7]  Piotr Dziurzanski,et al.  A Survey and Comparative Study of Hard and So Real-time Dynamic Resource Allocation Strategies for Multi / Many-core Systems , 2017 .

[8]  Donatas Siaudinis,et al.  Power Gating of the FlexCore Processor , 2010 .

[9]  Yingtao Jiang,et al.  On self-tuning networks-on-chip for dynamic network-flow dominance adaptation , 2013, 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

[10]  Amit Kumar Singh,et al.  HiMap: A hierarchical mapping approach for enhancing lifetime reliability of dark silicon manycore systems , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[11]  Hamid Sarbazi-Azad,et al.  Using task migration to improve non-contiguous processor allocation in NoC-based CMPs , 2013, J. Syst. Archit..

[12]  Iraklis Anagnostopoulos,et al.  Distributed run-time resource management for malleable applications on many-core platforms , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[13]  Wei Zhang,et al.  Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip , 2018, IEEE Transactions on Computers.

[14]  Santanu Chattopadhyay,et al.  Thermal-Aware Application Mapping Strategy for Network-on-Chip Based System Design , 2018, IEEE Transactions on Computers.

[15]  Karthikeyan Sankaralingam,et al.  Dark Silicon and the End of Multicore Scaling , 2012, IEEE Micro.

[16]  Michael C. Huang,et al.  Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip , 2013, Journal of Computer Science and Technology.

[17]  Jerome A. Rolia,et al.  Workload Analysis and Demand Prediction of Enterprise Data Center Applications , 2007, 2007 IEEE 10th International Symposium on Workload Characterization.

[18]  Gokhan Memik,et al.  Therma: Thermal-aware Run-time Thread Migration for Nanophotonic Interconnects , 2016, ISLPED.

[19]  Jung Ho Ahn,et al.  McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[20]  Anoop Gupta,et al.  The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.

[21]  Henry Hoffmann,et al.  Application heartbeats: a generic interface for specifying program performance and goals in autonomous computing environments , 2010, ICAC '10.

[22]  Mineo Takai,et al.  Parssec: A Parallel Simulation Environment for Complex Systems , 1998, Computer.

[23]  Amit Kumar Singh,et al.  Exploiting Dark Cores for Performance Optimization via Patterning for Many-core Chips in the Dark Silicon Era , 2018, 2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS).

[24]  Cristinel Ababei,et al.  Unified reliability estimation and management of NoC based chip multiprocessors , 2014, Microprocess. Microsystems.

[25]  Kevin Skadron,et al.  Temperature-aware microarchitecture: Modeling and implementation , 2004, TACO.

[26]  Axel Jantsch,et al.  adBoost: Thermal Aware Performance Boosting Through Dark Silicon Patterning , 2018, IEEE Transactions on Computers.

[27]  Sean R Eddy,et al.  What is dynamic programming? , 2004, Nature Biotechnology.

[28]  Pasi Liljeberg,et al.  Smart hill climbing for agile dynamic mapping in many-core systems , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[29]  Amit Kumar Singh,et al.  Bubble Budgeting: Throughput Optimization for Dynamic Workloads by Exploiting Dark Cores in Many Core Systems , 2016, IEEE Transactions on Computers.

[30]  Heba Khdr,et al.  Thermal constrained resource management for mixed ILP-TLP workloads in dark silicon chips , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).