VHDL implementation of feature-extraction algorithm for the PANDA electromagnetic calorimeter

The feature-extraction algorithm, developed for the digital front-end electronics of the electromagnetic calorimeter of the PANDA detector at the future FAIR facility, is implemented in VHDL for a commercial 16 bit 100 MHz sampling ADC. The use of modified firmware with the running on-line data-processing algorithm will allow to perform realistic performance studies of the calorimeter and test a trigger-less readout concept of the data acquisition for the PANDA experiment.