Digital Calibration of a Nonlinear S/H

Sample and hold (S/H) circuits exhibit a nonlinear behavior due to the input signal dependence of the sampling switch. In this paper, we develop a mixed signal model of this nonlinearity, where the need for a mixed signal description arises from the continuous-time input and sampled output of the S/H. The model is derived by employing a Volterra series expansion. Analysis of the model reveals that as the input signal passes through the S/H, its bandwidth expands, so the signal at the MOS switch output has a bandwidth two or three times larger than the input signal. Under the assumption that the signal at the MOS switch output is sampled above its Nyquist rate, a digital correction method is presented which relies on the theory of pth degree Volterra series inverses. An adaptive blind estimation technique working in tandem with the correction method is also derived for identifying the parameters characterizing the S/H nonlinearity. Numerical simulations are presented demonstrating that for oversampled input signals, the proposed digital calibration achieves a significant spurious free dynamic range (SFDR) improvement at a relatively modest computational cost.

[1]  Mohamed A. Y. Abdulla,et al.  Distortion Analysis in Analog Integrated Circuits , 2002 .

[2]  John Tsimbinos,et al.  Input Nyquist sampling suffices to identify and compensate nonlinear systems , 1998, IEEE Trans. Signal Process..

[3]  P. Hurst,et al.  A digital background calibration technique for time-interleaved analog-to-digital converters , 1998, IEEE J. Solid State Circuits.

[4]  A. Banerjee.  Convex Analysis and Optimization , 2006 .

[5]  Dan P. Scholnik.  Mixed-norm fir filter optimization using second-order cone programming , 2002, 2002 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[6]  M. Segami,et al.  A 3.3 V, 12b, 50MSample/s A/D converter in 0.6 /spl mu/m CMOS with over 80 dB SFDR , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[7]  Robert G. Meyer,et al.  Analysis and Design of Analog Integrated Circuits , 1993 .

[8]  John F. Spina,et al.  Sinusoidal analysis and modeling of weakly nonlinear circuits : with application to nonlinear interference effects , 1980 .

[9]  Terri S. Fiez,et al.  Prediction and Characterization of Frequency Dependent MOS Switch Linearity and the Design Implications , 2006, IEEE Custom Integrated Circuits Conference 2006.

[10]  P.J. Hurst,et al.  A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration , 2004, IEEE Journal of Solid-State Circuits.

[11]  Stephen H. Lewis,et al.  Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  D. A. George.  Continuous nonlinear systems , 1959 .

[13]  Alberto L. Sangiovanni-Vincentelli,et al.  Embedding Mixed-Signal Design in Systems-on-Chip , 2006, Proceedings of the IEEE.

[14]  P. Kumar,et al.  Theory and practice of recursive identification , 1985, IEEE Transactions on Automatic Control.

[15]  David A. Johns,et al.  Analog Integrated Circuit Design , 1996 .

[16]  Haruo Kobayashi,et al.  Explicit analysis of channel mismatch effects in time-interleaved ADC systems , 2001 .

[17]  Bernhard E. Boser,et al.  The Design of Sigma-Delta Modulation Analog-to-Digit a 1 Converters , 2004 .

[18]  Jesper Steensgaard,et al.  Bootstrapped low-voltage analog switches , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[19]  A. Abidi,et al.  A 3 . 3V 12b 50-MS / s A / D Converter in 0 . 6-m CMOS with over 80-dB SFDR , 2000 .

[20]  B. Murmann,et al.  A 12 b 75 MS/s pipelined ADC using open-loop residue amplification , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[21]  W. Frank.  Sampling requirements for Volterra system identification , 1996, IEEE Signal Processing Letters.

[22]  B. Leung,et al.  Distortion analysis of MOS track-and-hold sampling mixers using time-varying Volterra series , 1999 .

[23]  W. Hioe,et al.  Novel automatic tuning method of RC filters using a digital-DLL technique , 2004, IEEE Journal of Solid-State Circuits.

[24]  Patrick Satarzadeh,et al.  Bandwidth Mismatch Correction for a Two-Channel Time-Interleaved A/D Converter , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[25]  Paul R. Gray,et al.  A 1.5 V, 10-bit, 14 MS/s CMOS pipeline analog-to-digital converter , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[26]  Hannu Tenhunen,et al.  Performance analysis of sampling switches in voltage and frequency domains using Volterra series , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[27]  Robert G. Meyer,et al.  An engineering model for short-channel MOS devices , 1988 .

[28]  Stefan Tertinek,et al.  Reconstruction of Nonuniformly Sampled Bandlimited Signals Using a Differentiator–Multiplier Cascade , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[29]  Todd L. Brooks,et al.  A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR , 1997 .

[30]  R. de Figueiredo.  The Volterra and Wiener theories of nonlinear systems , 1982, Proceedings of the IEEE.

[31]  Gert Cauwenberghs,et al.  Adaptive digital correction of analog errors in MASH ADCs. I. Off-line and blind on-line calibration , 2000 .

[32]  Stephen P. Boyd,et al.  Applications of second-order cone programming , 1998 .

[33]  Stephen P. Boyd,et al.  Convex Optimization , 2004, Algorithms and Theory of Computation Handbook.

[34]  P. R. Gray,et al.  A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter , 1999, IEEE J. Solid State Circuits.

[35]  Stephen H. Lewis,et al.  Bandwidth Mismatch and Its Correction in Time-Interleaved Analog-to-Digital Converters , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[36]  Pierre Priouret,et al.  Adaptive Algorithms and Stochastic Approximations , 1990, Applications of Mathematics.

[37]  K. Bult,et al.  Analog design in deep sub-micron CMOS , 2000, Proceedings of the 26th European Solid-State Circuits Conference.

[38]  Alan B. Grebene,et al.  Analog Integrated Circuit Design , 1978 .

[39]  Bernard C. Levy,et al.  Adaptive blind calibration of timing offset and gain mismatch for two-channel time-interleaved ADCs , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.