Improved algorithms for hypergraph bipartitioning

Multilevel Fiduccia-Mattheyses (MLFM) hypergraph partitioning is a fundamental optimization in VLSI CAD physical design. The leading implementation, hMetis, has since 1997 proved itself substantially superior in both runtime and solution quality to even very recent work. In this work, we present two sets of results: (i) new techniques for flat FM-based hypergraph partitioning (which is the core of multilevel implementations), and (ii) a new multilevel implementation that offers leading-edge performance. Our new techniques for flat partitioning confirm the conjecture that specialized partitioning heuristics may be able to actively exploit fixed nodes in partitioning instances arising in the driving top-down placement context. Our FM variant is competitive with traditional FM on instances without terminals and considerably superior on instances with fixed nodes (i.e., arising during top-down placement). Our multilevel FM variant avoids several complex heuristics and non-trivial tunings that often lead to complex implementations; it achieves trade-offs between solution quality and run time that are comparable or better than those achieved by hMetis-1.5.3. We attempt to provide algorithm descriptions that are as detailed and unambiguous as possible, to allow replicability and speed improvements in future research.

[1]  Charles M. Fiduccia,et al.  A linear-time heuristic for improving network partitions , 1988, 25 years of DAC.

[2]  Brian W. Kernighan,et al.  A Procedure for Placement of Standard-Cell VLSI Circuits , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Gaetano Borriello,et al.  An evaluation of bipartitioning techniques , 1995, Proceedings Sixteenth Conference on Advanced Research in VLSI.

[4]  Andrew B. Kahng,et al.  Recent directions in netlist partitioning: a survey , 1995, Integr..

[5]  Dennis J.-H. Huang,et al.  On implementation choices for iterative improvement partitioning algorithms , 1995, Proceedings of EURO-DAC. European Design Automation Conference.

[6]  Shantanu Dutt,et al.  VLSI circuit partitioning by cluster-removal using iterative improvement techniques , 1996, ICCAD 1996.

[7]  S. Dutt,et al.  VLSI circuit partitioning by cluster-removal using iterative improvement techniques , 1996, Proceedings of International Conference on Computer Aided Design.

[8]  S. Dutt,et al.  Partitioning around roadblocks: tackling constraints with intermediate relaxations , 1997, ICCAD 1997.

[9]  Andrew B. Kahng,et al.  Multilevel circuit partitioning , 1997, DAC.

[10]  Shashi Shekhar,et al.  Multilevel hypergraph partitioning: application in VLSI domain , 1997, DAC.

[11]  Jason Cong,et al.  Large scale circuit partitioning with loose/stable net removal and signal flow based clustering , 1997, ICCAD 1997.

[12]  Andrew B. Kahng,et al.  Partitioning-based standard-cell global placement with an exact objective , 1997, ISPD '97.

[13]  Design of Experiments to Evaluate CAD Algorithms: Which Improvements Are Due to Improved Heuristic and Which Are Merely Due to Chance? , 1998 .

[14]  E.J. Aas,et al.  On multilevel circuit partitioning , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[15]  Charles J. Alpert,et al.  The ISPD98 circuit benchmark suite , 1998, ISPD '98.

[16]  C. K. Eem,et al.  An efficient iterative improvement technique for VLSI circuit partitioning using hybrid bucket structures , 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

[17]  Andrew B. Kahng,et al.  Partitioning with terminals: a “new” problem and new benchmarks , 1999, ISPD '99.

[18]  Jan-Ming Ho,et al.  An efficient two-level partitioning algorithm for VLSI circuits , 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

[19]  Andrew B. Kahng,et al.  Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning , 1999, ALENEX.

[20]  Andrew B. Kahng,et al.  Optimal partitioners and end-case placers for standard-cell layout , 1999, ISPD '99.

[21]  G. Karypis,et al.  Multilevel k-way hypergraph partitioning , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[22]  Andrew B. Kahng,et al.  Hypergraph partitioning with fixed vertices , 1999, DAC '99.

[23]  Andrew B. Kahng,et al.  Hypergraph partitioning for VLSI CAD: methodology for heuristic development, experimentation and reporting , 1999, DAC '99.

[24]  Vipin,et al.  Multilevel kway Hypergraph Partitioning * , 1999 .

[25]  Shashi Shekhar,et al.  Multilevel hypergraph partitioning: applications in VLSI domain , 1999, IEEE Trans. Very Large Scale Integr. Syst..