DB4HLS: A Database of High-Level Synthesis Design Space Explorations

High-Level Synthesis (HLS) frameworks allow to easily specify a large number of variants of the same hardware design by only acting on optimization directives. Nonetheless, the hardware synthesis of implementations for all possible combinations of directive values is impractical even for simple designs. Addressing this shortcoming, many HLS Design Space Exploration (DSE) strategies have been proposed to devise directive settings leading to high-quality implementations while limiting the number of synthesis runs. All these works require considerable efforts to validate the proposed strategies and/or to build the knowledge base employed to tune abstract models, as both tasks mandate the syntheses of large collections of implementations. Currently, such data gathering is performed ad-hoc, a) leading to a lack of standardization, hampering comparisons between DSE alternatives, and b) posing a very high burden to researchers willing to develop novel DSE strategies. Against this backdrop, we here introduce DB4HLS, a database of exhaustive HLS explorations comprising more than 100000 design points collected over 4 years of synthesis time. The open structure of DB4HLS allows the incremental integration of new DSEs, which can be easily defined with a dedicated domainspecific language. We think that of our database, available at https://www.db4hls.inf.usi.ch/, will be a valuable tool for the research community investigating automated strategies for the optimization of HLS-based hardware designs.

[1]  Hiroyuki Tomiyama,et al.  CHStone: A benchmark program suite for practical C-based high-level synthesis , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[2]  Yun Liang,et al.  Design space exploration of multiple loops on FPGAs using high level synthesis , 2014, 2014 IEEE 32nd International Conference on Computer Design (ICCD).

[3]  Laura Pozzi,et al.  Lattice-Traversing Design Space Exploration for High Level Synthesis , 2018, 2018 IEEE 36th International Conference on Computer Design (ICCD).

[4]  Yuan Zhou,et al.  Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs , 2018, FPGA.

[5]  Gu-Yeon Wei,et al.  MachSuite: Benchmarks for accelerator design and customized architectures , 2014, 2014 IEEE International Symposium on Workload Characterization (IISWC).

[6]  Vittorio Zaccaria,et al.  SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Ole Tange,et al.  GNU Parallel: The Command-Line Power Tool , 2011, login Usenix Mag..

[8]  Benjamin Carrión Schäfer,et al.  S2CBench: Synthesizable SystemC Benchmark Suite for High-Level Synthesis , 2014, IEEE Embedded Systems Letters.

[9]  Laura Pozzi,et al.  Cluster-Based Heuristic for High Level Synthesis Design Space Exploration , 2018, IEEE Transactions on Emerging Topics in Computing.

[10]  Giovanni Ansaloni,et al.  Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis , 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Zi Wang,et al.  Efficient and Robust High-Level Synthesis Design Space Exploration through offline Micro-kernels Pre-characterization , 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[12]  Luca P. Carloni,et al.  On learning-based methods for design-space exploration with High-Level Synthesis , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).