Scheduling time-constrained instructions on pipelined processors

In this work we investigate the problem of scheduling instructions on idealized microprocessors with multiple pipelines, in the presence of precedence constraints, release-times, deadlines, and latency constraints. A latency of <italic>l<subscrpt>ij</subscrpt></italic> specifies that there must be at least <italic>l<subscrpt>ij</subscrpt></italic> time-steps between the completion time of instruction <italic>i</italic> and the start time of instruction <italic>j</italic>. A latency of <italic>l<subscrpt>ij</subscrpt></italic>=−1 can be used to specify that <italic>j</italic> may be scheduled concurrently with <italic>i</italic> but not earlier. We present a generic algorithm that runs in <italic>O</italic>(<italic>n</italic><supscrpt>2</supscrpt>log<italic>n</italic>α(<italic>n</italic>)+<italic>ne</italic>) time, given<italic>n</italic> instructions and <italic>e</italic> edges in the precedence DAG, where α(<italic>n</italic>) is the functional inverse of the Ackermann function. Our algorithm can be used to construct feasible schedules for various classes of instances, including instances with the following configurations: (1) one pipeline, with individual release-times and deadlines and where the latencies between instructions are restricted to 0 and 1; (2) <italic>m</italic> pipelines, with individual release-times and deadlines, and monotone-interval order precedences; (3) two pipelines with latencies of −1 or 0, and release-times and deadlines; (4) one pipeline, latencies of 0 or 1 and individual processing times that are at least one; (5) <italic>m</italic> pipelines, intree precedences, constant latencies, and deadlines; (6) <italic>m</italic> pipelines, outtree precedences, constant latencies, and release-times. For instances with deadlines, optimal schedules that minimize the maximal tardiness can be constructed using binary search, in <italic>O</italic>(log <italic>n</italic>) iterations of our algorithm. We obtain our results using backward scheduling, a very general relaxation method, which extends, unifies, and clarifies many previous results on instruction scheduling for pipelined and parallel machines.

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