Model-based Performance Evaluation of Dynamic Partial Reconfigurable Datapaths for FPGA-based Systems

Dynamic partial-reconfigurable (DPR) FPGAs have the property that all or part of their functionality can be time-multiplexed at run-time. This is achieved by dynamically transferring partial configuration bitstreams from off-chip memory to FPGA configuration memory via a specialized datapath. The performance of this datapath can have a significant impact on overall system performance and should be considered early in the design cycle. Unfortunately, performance measures for such systems can typically be determined only after development. Such measures are heavily dependent upon the detailed characteristics of the datapath and on the particular workload imposed on the system during measurement and thus can only be used to make predictions for systems similar to that used for initial measurements. In this chapter, we outline an approach to model the DPR datapath early in the design cycle using queueing networks. This modeling approach is essential for experimenting with system parameters and for providing statistical insight into the effectiveness of candidate architectures. A case study is provided to demonstrate the usefulness and flexibility of the modeling scheme.