PDP scan driver with NVDMOS and RESURF PLDMOS

A high voltage CMOS IC technology by using 25/spl mu/m thick epitaxy based on 1.2/spl mu/m standard CMOS process has been developed. In this technology, LDMOS and VDMOS are fabricated together. Junction isolation is used to isolate VDMOS from LDMOS, low voltage CMOS, and other VDMOSs. Test results show that the rise time and the fall time of the output stage is about 45ns and 50ns, respectively. For the simplicity of the technology, the cost is saved.

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