An analog programmable multi-dimensional radial basis function based classifier

A compact analog programmable multi-dimensional radial basis function (RBF) based classifier is demonstrated. The probability distribution of each feature in the templates modeled by a Gaussian function is approximately realized by the transfer characteristics of a floating-gate bump circuit. The maximum likelihood, the mean, and the variance can be inde- pendently programmed. By cascading these floating-gate bump circuits, the transfer characteristics approximate a multivariate Gaussian function with a diagonal covariance matrix. An array of these circuits constitute a compact multi-dimensional RBF- based classifier. When followed by a winner-take-all circuit, the RBF-based classifier forms an analog vector quantizer. We use receiver operating characteristic curves and equal error rate to evaluate the performance of our analog classifiers. We show that the analog classifier performance is comparable to that of digital counterparts. The proposed approach can be at least two orders of magnitude more power efficient than the digital microprocessors at the same task.

[1]  Jui-Ming Chang,et al.  A Gaussian synapse circuit for analog VLSI neural networks , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[2]  David V. Anderson,et al.  A floating-gate vector-quantizer , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[3]  P. Hasler,et al.  Adaptive Algorithm Using Hot-Electron Injection for Programming Analog Computational Memory Elements Within 0.2% of Accuracy Over 3.5 Decades , 2006, IEEE Journal of Solid-State Circuits.

[4]  Tzi-Dar Chiueh,et al.  A tunable Gaussian/square function computation circuit for analog neural networks , 1998 .

[5]  Paul Hasler,et al.  Continuous-time feedback in floating-gate MOS circuits , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[6]  Sandro Ridella,et al.  Digital implementation of hierarchical vector quantization , 2003, IEEE Trans. Neural Networks.

[7]  T. Delbruck.  'Bump' circuits for computing similarity and dissimilarity of analog voltages , 1991, IJCNN-91-Seattle International Joint Conference on Neural Networks.

[8]  R. Genov,et al.  175 GMACS/mW Charge-Mode Adiabatic Mixed-Signal Array Processor , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[9]  D.V. Anderson,et al.  Analog floating-gate, on-chip auditory sensing system interfaces , 2005, IEEE Sensors Journal.

[10]  Tadashi Shibata,et al.  Analog Soft-Pattern-Matching Classifier using Floating-Gate MOS Technology , 2001, NIPS.

[11]  Paul M. Chau,et al.  A radial basis function neurocomputer implemented with analog VLSI circuits , 1992, [Proceedings 1992] IJCNN International Joint Conference on Neural Networks.

[12]  T. Shibata,et al.  A general-purpose vector-quantization processor employing two-dimensional bit-propagating winner-take-all , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[13]  Miguel Figueroa,et al.  A Silicon Primitive for Competitive Learning , 2000, NIPS.

[14]  Paul E. Hasler,et al.  A precision CMOS amplifier using floating-gates for offset cancellation , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[15]  Venkatesh Srinivasan,et al.  A 531 nW/MHz, 128/spl times/32 current-mode programmable analog vector-matrix multiplier with over two decades of linearity , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[16]  M. Masmoudi,et al.  A subthreshold mode programmable implementation of the Gaussian function for RBF neural networks applications , 2002, Proceedings of the IEEE Internatinal Symposium on Intelligent Control.

[17]  Stamatis Vassiliadis,et al.  Sandblaster Low Power DSP , 2004 .

[18]  Paul Hasler,et al.  A programmable continuous-time floating-gate Fourier processor , 2001 .

[19]  G. Cauwenberghs,et al.  A low-power CMOS analog vector quantizer , 1997 .

[20]  Paul E. Hasler,et al.  Correlation learning rule in floating-gate pFET synapses , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).