FlexRAM: Toward an advanced Intelligent Memory system
暂无分享,去创建一个
Seung-Moon Yoo | Josep Torrellas | Diana Franklin | Wei Huang | Yi Kang | Vinh Vi Lam | Pratap Pattnaik | Zhenzhou Ge | D. Franklin | V. Lam | P. Pattnaik | J. Torrellas | Wei Huang | Seung-Moon Yoo | Y. Kang | Zhenzhou Ge
[1] Frederic T. Chong,et al. Active pages: a computation model for intelligent memory , 1998, ISCA.
[2] Robert J. Fowler,et al. MINT: a front end for efficient simulation of shared-memory multiprocessors , 1994, Proceedings of International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems.
[3] William J. Dally,et al. Smart Memories: a modular reconfigurable architecture , 2000, ISCA '00.
[4] Christoforos E. Kozyrakis,et al. A case for intelligent RAM , 1997, IEEE Micro.
[5] Jaewook Shin,et al. Mapping Irregular Applications to DIVA, a PIM-based Data-Intensive Architecture , 1999, ACM/IEEE SC 1999 Conference (SC'99).
[6] Noah Treuhaft,et al. Scalable Processors in the Billion-Transistor Era: IRAM , 1997, Computer.
[7] Michael Stonebraker,et al. Optimization of parallel query execution plans in XPRS , 2005, Distributed and Parallel Databases.
[8] D. Reid,et al. 450 MHz PowerPC/sup TM/ microprocessor with enhanced instruction set and copper interconnect , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
[9] Fong Pong,et al. Missing the Memory Wall: The Case for Processor/Memory Integration , 1996, 23rd Annual International Symposium on Computer Architecture (ISCA'96).
[10] Neal Cardwell,et al. Evaluation of Existing Architectures in IRAM Systems , 1998 .
[11] Vivek Sarkar,et al. Baring It All to Software: Raw Machines , 1997, Computer.
[12] Kiyoo Itoh,et al. Limitations and challenges of multigigabit DRAM chip design , 1997, IEEE J. Solid State Circuits.
[13] William J. Dally,et al. A bandwidth-efficient architecture for media processing , 1998, Proceedings. 31st Annual ACM/IEEE International Symposium on Microarchitecture.
[14] J. A. Gasbarro. The Rambus memory system , 1995, Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing.
[15] Hector Sanchez,et al. A 2.2 W, 80 MHz superscalar RISC microprocessor , 1994 .
[16] P.M. Kogge,et al. Pursuing a petaflop: point designs for 100 TF computers using PIM technologies , 1996, Proceedings of 6th Symposium on the Frontiers of Massively Parallel Computation (Frontiers '96).
[17] Thomas H. Lee,et al. A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM , 1994, IEEE J. Solid State Circuits.
[18] E. Myers,et al. Basic local alignment search tool. , 1990, Journal of molecular biology.
[19] Josep Torrellas,et al. A direct-execution framework for fast and accurate simulation of superscalar processors , 1998, Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192).
[20] Richard Crisp,et al. Direct RAMbus technology: the new main memory standard , 1997, IEEE Micro.
[21] Mark Horowitz,et al. PLL design for a 500 MB/s interface , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[22] Michael C. Huang,et al. FlexRAM Architecture Design Parameters , 2002 .
[23] Lee,et al. Highly Manufacturable 1Gb SDRAM , 1997, 1997 Symposium on VLSI Technology.
[24] Josep Torrellas,et al. Automatically mapping code on an intelligent memory architecture , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.