Image sensor parasitism insensitiveness simulation accumulator and time sequence control method

The invention relates to the field of integrated circuit design. In order to improve a simulation accumulator applied to a TDI CIS, greatly increase effective accumulative levels of the accumulator, and not increase the area and the power consumption of a circuit, the invention adopts the technical scheme as follows: the image sensor parasitic insensitiveness simulation accumulator comprises an operational amplifier, N+1 levels of integrators, a sampling switch and integrating switches, each level of integrator consists of four integrating switches, two integrating capacitors and two reset switches; a decoupling switch is arranged in each level of integrator; the decoupling switch is connected between upper electrode plates of the two integrating capacitors. The technical scheme provided by the invention is mainly applied to the integrated circuit design.