Timing speculation and adaptive reliable overclocking techniques for aggressive computer systems

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv CHAPTER

[1]  Avi Mendelson,et al.  Analysis of Thermal Monitor features of the Intel® Pentium® M Processor , 2004 .

[2]  Hiroshi Iwai,et al.  CHALLENGES FOR FUTURE SEMICONDUCTOR MANUFACTURING , 2006 .

[3]  Ted Kehl,et al.  Hardware self-tuning and circuit performance monitoring , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

[4]  Arun K. Somani,et al.  SSD: an affordable fault tolerant architecture for superscalar processors , 2001, Proceedings 2001 Pacific Rim International Symposium on Dependable Computing.

[5]  Augustus K. Uht,et al.  Uniprocessor performance enhancement through adaptive clock frequency control , 2005, IEEE Transactions on Computers.

[6]  S. Zafar,et al.  A Model for Negative Bias Temperature Instability in Oxide and High κ pFETs , 2007, 2007 IEEE International Conference on Integrated Circuit Design and Technology.

[7]  Edward J. McCluskey,et al.  Which concurrent error detection scheme to choose ? , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[8]  S. Satoh,et al.  Simple method for estimating neutron-induced soft error rates based on modified BGR model , 1999, IEEE Electron Device Letters.

[9]  B. Narasimham,et al.  Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies , 2007, IEEE Transactions on Nuclear Science.

[10]  Cristian Constantinescu,et al.  Trends and Challenges in VLSI Circuit Reliability , 2003, IEEE Micro.

[11]  Viswanathan Subramanian,et al.  SEU Mitigation Techniques for Microprocessor Control Logic , 2006, 2006 Sixth European Dependable Computing Conference.

[12]  Josep Torrellas,et al.  EVAL: Utilizing processors with variation-induced timing errors , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

[13]  D. Blaauw,et al.  Opportunities and challenges for better than worst-case design , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[14]  Robert H. Dennard,et al.  CMOS scaling for high performance and low power-the next ten years , 1995, Proc. IEEE.

[15]  Huiyang Zhou,et al.  Dual-core execution: building a highly scalable single-thread instruction window , 2005, 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05).

[16]  Robert P. Colwell.  The Zen of overclocking , 2004, Computer.

[17]  H. Hughes,et al.  Radiation effects and hardening of MOS technology: devices and circuits , 2003 .

[18]  Shekhar Y. Borkar,et al.  Design challenges of technology scaling , 1999, IEEE Micro.

[19]  S. Naffziger,et al.  Power and temperature control on a 90-nm Itanium family processor , 2006, IEEE Journal of Solid-State Circuits.

[20]  Lloyd W. Massengill,et al.  Impact of scaling on soft-error rates in commercial microprocessors , 2002 .

[21]  P. Hazucha,et al.  Cosmic-ray soft error rate characterization of a standard 0.6-/spl mu/m CMOS process , 2000, IEEE Journal of Solid-State Circuits.

[22]  Todd M. Austin,et al.  SimpleScalar: An Infrastructure for Computer System Modeling , 2002, Computer.

[23]  Martin Burtscher,et al.  Bridging the processor-memory performance gap with 3D IC technology , 2005, IEEE Design & Test of Computers.

[24]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[25]  Margaret Martonosi,et al.  Dynamic thermal management for high-performance microprocessors , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[26]  M. Ieong,et al.  Silicon Device Scaling to the Sub-10-nm Regime , 2004, Science.

[27]  Yuan Taur,et al.  Device scaling limits of Si MOSFETs and their application dependencies , 2001, Proc. IEEE.

[28]  Arvind Kumar,et al.  Silicon CMOS devices beyond scaling , 2006, IBM J. Res. Dev..

[29]  Chin-Long Chen,et al.  Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review , 1984, IBM J. Res. Dev..

[30]  Kevin Skadron,et al.  Temperature-aware microarchitecture , 2003, ISCA '03.

[31]  Karthikeyan Sankaralingam,et al.  SimpleScalar Simulation of the PowerPC Instruction Set Architecture , 2001 .

[32]  Sarita V. Adve,et al.  AS SCALING THREATENS TO ERODE RELIABILITY STANDARDS, LIFETIME RELIABILITY MUST BECOME A FIRST-CLASS DESIGN CONSTRAINT. MICROARCHITECTURAL INTERVENTION OFFERS A NOVEL WAY TO MANAGE LIFETIME RELIABILITY WITHOUT SIGNIFICANTLY SACRIFICING COST AND PERFORMANCE , 2005 .

[33]  Babak Falsafi,et al.  Reunion: Complexity-Effective Multicore Redundancy , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[34]  R. Chau,et al.  In search of "Forever," continued transistor scaling one new material at a time , 2005, IEEE Transactions on Semiconductor Manufacturing.

[35]  David J. Sager,et al.  The microarchitecture of the Pentium 4 processor , 2001 .

[36]  Joel S. Emer,et al.  Techniques to reduce the soft error rate of a high-performance microprocessor , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[37]  Josep Torrellas,et al.  Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking , 2007, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007).

[38]  Tong Liu,et al.  Performance improvement with circuit-level speculation , 2000, MICRO 33.

[39]  Paul D. Franzon,et al.  FreePDK: An Open-Source Variation-Aware Design Kit , 2007, 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07).

[40]  Thomas D. Burd,et al.  The simulation and evaluation of dynamic voltage scaling algorithms , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[41]  Philip Levis,et al.  Policies for dynamic clock scheduling , 2000, OSDI.

[42]  Krste Asanovic,et al.  Reducing power density through activity migration , 2003, ISLPED '03.

[43]  R.C. Baumann,et al.  Radiation-induced soft errors in advanced semiconductor technologies , 2005, IEEE Transactions on Device and Materials Reliability.

[44]  Todd M. Austin,et al.  The SimpleScalar tool set, version 2.0 , 1997, CARN.

[45]  Arif Merchant,et al.  Analysis of a Control Mechanism for a Variable Speed Processor , 1996, IEEE Trans. Computers.

[46]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.

[47]  Yehea I. Ismail,et al.  Engineering over-clocking: reliability-performance trade-offs for high-performance register files , 2005, 2005 International Conference on Dependable Systems and Networks (DSN'05).

[48]  K. Sundaramoorthy,et al.  Slipstream processors: improving both performance and fault tolerance , 2000, SIGP.

[49]  A. Chandrakasan,et al.  An efficient controller for variable supply-voltage low power processing , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[50]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[51]  Viswanathan Subramanian,et al.  Conjoined Pipeline: Enhancing Hardware Reliability and Performance through Organized Pipeline Redundancy , 2008, 2008 14th IEEE Pacific Rim International Symposium on Dependable Computing.

[52]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[53]  Jordi Suñé,et al.  Interplay of voltage and temperature acceleration of oxide breakdown for ultra-thin gate oxides , 2002 .

[54]  Trevor N. Mudge,et al.  Power: A First-Class Architectural Design Constraint , 2001, Computer.

[55]  R.W. Brodersen,et al.  A dynamic voltage scaled microprocessor system , 2000, IEEE Journal of Solid-State Circuits.

[56]  J. Torrellas,et al.  VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects , 2008, IEEE Transactions on Semiconductor Manufacturing.

[57]  Huiyang Zhou,et al.  A case for fault tolerance and performance enhancement using chip multi-processors , 2006, IEEE Computer Architecture Letters.

[58]  Mona Attariyan,et al.  Low-Cost Protection for SER Upsets and Silicon Defects , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[59]  A. H. Johnston.  Radiation effects in advanced microelectronics technologies , 1997 .

[60]  Luigi Carro,et al.  Synthesis of an 8051-Like Micro-Controller Tolerant to Transient Faults , 2000, J. Electron. Test..

[61]  Kimberly D. Emerson.  Asynchronous design-an interesting alternative , 1997, Proceedings Tenth International Conference on VLSI Design.

[62]  Sanjay J. Patel,et al.  Characterizing the effects of transient faults on a high-performance processor pipeline , 2004, International Conference on Dependable Systems and Networks, 2004.

[63]  Todd M. Austin,et al.  DIVA: a reliable substrate for deep submicron microarchitecture design , 1999, MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture.

[64]  Ivan E. Sutherland,et al.  The counterflow pipeline processor architecture , 1994, IEEE Design & Test of Computers.

[65]  Michael L. Scott,et al.  Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling , 2002, Proceedings Eighth International Symposium on High Performance Computer Architecture.

[66]  J-C. Laprie,et al.  DEPENDABLE COMPUTING AND FAULT TOLERANCE : CONCEPTS AND TERMINOLOGY , 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing, 1995, ' Highlights from Twenty-Five Years'..

[67]  Scott Hauck,et al.  Asynchronous design methodologies: an overview , 1995, Proc. IEEE.

[68]  P.N. Sanda,et al.  IBM z990 soft error detection and recovery , 2005, IEEE Transactions on Device and Materials Reliability.

[69]  David Blaauw,et al.  Error analysis for the support of robust voltage scaling , 2005, Sixth international symposium on quality electronic design (isqed'05).

[70]  Robert K. Brayton,et al.  Minimum padding to satisfy short path constraints , 1993, ICCAD.

[71]  Nader Vasseghi,et al.  The Mips R4000 processor , 1992, IEEE Micro.

[72]  Kevin Skadron,et al.  An Improved Block-Based Thermal Model in HotSpot 4.0 with Granularity Considerations , 2007 .

[73]  Eric Rotenberg,et al.  AR-SMT: a microarchitectural approach to fault tolerance in microprocessors , 1999, Digest of Papers. Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing (Cat. No.99CB36352).

[74]  Arun K. Somani,et al.  On-line integrity monitoring of microprocessor control logic , 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

[75]  Josep Torrellas,et al.  ReCycle:: pipeline adaptation to tolerate process variation , 2007, ISCA '07.

[76]  Arun K. Somani,et al.  Soft error sensitivity characterization for microprocessor dependability enhancement strategy , 2002, Proceedings International Conference on Dependable Systems and Networks.

[77]  Arun K. Somani,et al.  REESE: a method of soft error detection in microprocessors , 2001, 2001 International Conference on Dependable Systems and Networks.

[78]  Martin Burtscher,et al.  Future execution: A prefetching mechanism that uses multiple cores to speed up single threads , 2006, TACO.

[79]  James D. Meindl,et al.  Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration , 2002, IEEE J. Solid State Circuits.

[80]  Sanjay Pant,et al.  A self-tuning DVS processor using delay-error detection and correction , 2005, IEEE Journal of Solid-State Circuits.

[81]  David Blaauw,et al.  Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation , 2003, MICRO.

[82]  R.H. Dennard,et al.  Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions , 1974, Proceedings of the IEEE.

[83]  Mikel Anton Bezdek,et al.  Utilizing timing error detection and recovery to dynamically improve superscalar processor performance , 2006 .

[84]  Shubhendu S. Mukherjee,et al.  Transient fault detection via simultaneous multithreading , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[85]  Todd M. Austin,et al.  A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor , 2003, MICRO.

[86]  Dragan Maksimovic,et al.  Closed-loop adaptive voltage scaling controller for standard-cell ASICs , 2002, ISLPED '02.

[87]  Sanjay J. Patel,et al.  ReStore: symptom based soft error detection in microprocessors , 2005, 2005 International Conference on Dependable Systems and Networks (DSN'05).

[88]  Viswanathan Subramanian,et al.  Managing the Impact of On-chip Temperature on the Lifetime Reliability of Reliably Overclocked Systems , 2009, 2009 Second International Conference on Dependability.

[89]  Vivek De,et al.  Design and reliability challenges in nanometer technologies , 2004, Proceedings. 41st Design Automation Conference, 2004..

[90]  G. Wolrich,et al.  A high performance floating point coprocessor , 1984, IEEE Journal of Solid-State Circuits.

[91]  Wayne Luk,et al.  Dynamic clock-frequencies for FPGAs , 2006, Microprocess. Microsystems.

[92]  Kevin Skadron,et al.  Temperature-aware microarchitecture: Modeling and implementation , 2004, TACO.

[93]  Viswanathan Subramanian,et al.  Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning , 2007, 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07).

[94]  Jose Renau,et al.  Effective Optimistic-Checker Tandem Core Design through Architectural Pruning , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[95]  Josep Torrellas,et al.  Blueshift: Designing processors for timing speculation from the ground up. , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[96]  Erven Rohou,et al.  Dynamically Managing Processor Temperature and Power , 1999 .

[97]  Sani R. Nassif,et al.  Modeling and forecasting of manufacturing variations , 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

[98]  Allan Hartstein,et al.  The optimum pipeline depth for a microprocessor , 2002, ISCA.