Conception d'un composant matériel réutilisable flexible pour la transformation en ondelettes 2D Design of a flexible, re-usable hardware component for the 2D discrete wavelet transform

and key words This paper deals with the implementation of the 2D discrete wavelet transform in the form of a reusable, flexible hardware component. This component is compliant with the JPEG2000 standard and targets a variety of embedded imaging applications. A novel design methodology based on the emerging high-level synthesis tools allowed us to achieve a high degree of flexibility in the specification and synthesis of this component. Customization of functional parameters is supported (choice of the lifting-based filter bank, number of decomposition levels) as well as communication constraints (pixel

[1]  John B. Shoven,et al.  I , Edinburgh Medical and Surgical Journal.

[2]  P. Six,et al.  Cathedral-II: A Silicon Compiler for Digital Signal Processing , 1986, IEEE Design & Test of Computers.

[3]  I. Daubechies Orthonormal bases of compactly supported wavelets , 1988 .

[4]  Stéphane Mallat,et al.  A Theory for Multiresolution Signal Decomposition: The Wavelet Representation , 1989, IEEE Trans. Pattern Anal. Mach. Intell..

[5]  Claude Gasquet,et al.  Analyse de Fourier et applications : filtrage, calcul numérique, ondelettes , 1990 .

[6]  Michel Barlaud,et al.  Image coding using wavelet transform , 1992, IEEE Trans. Image Process..

[7]  Daniel D. Gajski,et al.  High ― Level Synthesis: Introduction to Chip and System Design , 1992 .

[8]  I. Daubechies,et al.  Biorthogonal bases of compactly supported wavelets , 1992 .

[9]  Hugo De Man,et al.  Modeling multidimensional data and control flow , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[10]  Olivier Sentieys,et al.  GAUT: An architectural synthesis tool for dedicated signal processors , 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.

[11]  Doran Wilde,et al.  Regular array synthesis using ALPHA , 1994, Proceedings of IEEE International Conference on Application Specific Array Processors (ASSAP'94).

[12]  Doran Wilde,et al.  The ALPHA language , 1994 .

[13]  Raul Camposano Behavioral synthesis , 1995, IEEE Design & Test of Computers.

[14]  Chaitali Chakrabarti,et al.  Architectures for wavelet transforms: A survey , 1996, J. VLSI Signal Process..

[15]  Truong Q. Nguyen,et al.  Wavelets and filter banks , 1996 .

[16]  Christophe Latry,et al.  Selection of the SPOT5 image compression algorithm , 1998, Optics + Photonics.

[17]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[18]  I. Daubechies,et al.  Factoring wavelet transforms into lifting steps , 1998 .

[19]  John P. Elliott Understanding Behavioral Synthesis , 1999, Springer US.

[20]  Hugo De Man,et al.  An efficient VLSI architecture for 2-D wavelet image coding with novel image scan , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[21]  John P. Elliott Understanding Behavioral Synthesis: A Practical Guide to High-Level Design , 1999 .

[22]  Catherine Lambert-Nebout,et al.  Status of onboard image compression for CNES space missions , 1999, Optics & Photonics.

[23]  Grant Martin,et al.  Surviving the SOC Revolution , 1999, Springer US.

[24]  Nong Fan,et al.  Usage-based characterization of complex functional blocks for reuse in behavioral synthesis , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

[25]  Chaitali Chakrabarti,et al.  A VLSI architecture for lifting-based wavelet transform , 2000, 2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528).

[26]  Hugo De Man,et al.  Formalized three-layer system-level model and reuse methodology for embedded data-dominated applications , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[27]  Ahmed Amine Jerraya,et al.  Efficient integration of behavioral synthesis within existing design flows , 2000, ISSS '00.

[28]  H. De Man,et al.  Formalized three-layer system-level reuse model and methodology for embedded data-dominated applications , 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

[29]  Emmanuel Casseau,et al.  Behavioral Virtual Components for Embedded Image Compression Systems , 2000 .

[30]  Alberto L. Sangiovanni-Vincentelli,et al.  System-level design: orthogonalization of concerns andplatform-based design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[31]  Amer Baghdadi,et al.  A generic wrapper architecture for multi-processor SoC cosimulation and design , 2001, CODES '01.

[32]  John V. McCanny,et al.  Design of Silicon IP Cores for Biorthogonal Wavelet Transforms , 2001, J. VLSI Signal Process..

[33]  Luciano Lavagno,et al.  A hardware/software co-design flow and IP library based on simulink , 2001, DAC '01.

[34]  E. Martin,et al.  4 - Conception optimisée d'architectures en précision finie pour les applications de traitement du signal , 2001 .

[35]  M.D. Adams,et al.  Wavelet transforms in the JPEG-2000 standard , 2001, 2001 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (IEEE Cat. No.01CH37233).

[36]  G. A Theory for Multiresolution Signal Decomposition : The Wavelet Representation , 2004 .