Compact Test Pattern Selection for Small Delay Defect

This letter proposes an algorithm that selects a small number of test patterns for small delay defects from a large N-detect test set. This algorithm uses static upper and lower bound analysis to quickly estimate the sensitized path length so that the central processing unit (CPU) time can be reduced. By ignoring easy faults, only a partial fault dictionary, instead of a complete fault dictionary, is built for test pattern selection. Experimental results on large International Test Conference benchmark circuits show that, with very similar quality, the selected test set is 46% smaller and the CPU time is 42% faster than that of timing-aware automated test pattern generation (ATPG). With the proposed selection algorithm, small delay defect test sets are no longer very expensive to apply.

[1]  Edward J. McCluskey,et al.  Delay defect screening using process monitor structures , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[2]  Toshiyuki Maeda,et al.  Recognition of Sensitized Longest Paths in Transition Delay Test , 2006, 2006 IEEE International Test Conference.

[3]  Mark Mohammad Tehranipoor,et al.  A novel hybrid method for SDD pattern grading and selection , 2010, 2010 28th VLSI Test Symposium (VTS).

[4]  Mark Mohammad Tehranipoor,et al.  Test-Pattern Grading and Pattern Selection for Small-Delay Defects , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[5]  Xijiang Lin,et al.  Test Generation for Timing-Critical Transition Faults , 2007, 16th Asian Test Symposium (ATS 2007).

[6]  Irith Pomeranz,et al.  Selecting High-Quality Delay Tests for Manufacturing Test and Debug , 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[7]  Xiaoqing Wen,et al.  A Framework of High-quality Transition Fault ATPG for Scan Circuits , 2006, 2006 IEEE International Test Conference.

[8]  Camelia Hora,et al.  Systematic defects in deep sub-micron technologies , 2004, 2004 International Conferce on Test.

[9]  Chen Wang,et al.  Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects , 2006, 2006 15th Asian Test Symposium.

[10]  Michael S. Hsiao,et al.  ALAPTF: a new transition fault model and the ATPG algorithm , 2004, 2004 International Conferce on Test.

[11]  Mark Mohammad Tehranipoor,et al.  Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects , 2008, 2008 IEEE International Test Conference.

[12]  Weiping Shi,et al.  K longest paths per gate (KLPG) test generation for scan-based sequential circuits , 2004, 2004 International Conferce on Test.

[13]  Y. Sato,et al.  Evaluation of the statistical delay quality model , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[14]  Irith Pomeranz,et al.  On generating high quality tests for transition faults , 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

[15]  Narendra Devta-Prasanna,et al.  Effective and Efficient Test Pattern Generation for Small Delay Defect , 2009, 2009 27th IEEE VLSI Test Symposium.