Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOS

Active conduction modulation techniques are demonstrated in a fully integrated multi-ratio switched-capacitor voltage regulator with hysteretic control, implemented in 22nm tri-gate CMOS with high-density MIM capacitor. We present (i) an adaptive switching frequency and switch-size scaling scheme for maximum efficiency tracking across a wide range voltages and currents, governed by a frequency-based control law that is experimentally validated across multiple dies and temperatures, and (ii) a simple active ripple mitigation technique to modulate gate drive of select MOSFET switches effectively in all conversion modes. Efficiency boosts upto 15% at light loads are measured under light load conditions. Load-independent output ripple of <;50mV is achieved, enabling fewer interleaving. Testchip implementations and measurements demonstrate ease of integration in SoC designs, power efficiency benefits and EMI/RFI improvements.

[1]  R. Dennard,et al.  A fully-integrated switched-capacitor 2∶1 voltage converter with regulation capability and 90% efficiency at 2.3A/mm2 , 2010, 2010 Symposium on VLSI Circuits.

[2]  Rinkle Jain,et al.  A novel control technique to eliminate output-voltage-ripple in switched-capacitor DC-DC converters , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[3]  Elad Alon,et al.  Design Techniques for Fully Integrated Switched-Capacitor DC-DC Converters , 2011, IEEE Journal of Solid-State Circuits.

[4]  G. Curello,et al.  A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications , 2012, 2012 International Electron Devices Meeting.

[5]  Michael D. Seeman,et al.  Analysis and Optimization of Switched-Capacitor DC–DC Converters , 2008 .

[6]  Ramesh Harjani,et al.  Fully Integrated Capacitive DC–DC Converter With All-Digital Ripple Mitigation Technique , 2013, IEEE Journal of Solid-State Circuits.

[7]  Anantha Chandrakasan,et al.  A Fully-Integrated Switched-Capacitor Step-Down DC-DC Converter With Digital Capacitance Modulation in 45 nm CMOS , 2010, IEEE Journal of Solid-State Circuits.

[8]  Hoi Lee,et al.  An SC Voltage Doubler with Pseudo-Continuous Output Regulation Using a Three-Stage Switchable Opamp , 2007, IEEE Journal of Solid-State Circuits.

[9]  Seth Sanders,et al.  A 200mA switched capacitor voltage regulator on 32nm CMOS and regulation schemes to enable DVFS , 2011, Proceedings of the 2011 14th European Conference on Power Electronics and Applications.

[10]  Michael D. Seeman,et al.  The Road to Fully Integrated DC–DC Conversion via the Switched-Capacitor Approach , 2013, IEEE Transactions on Power Electronics.

[11]  James Tschanz,et al.  8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[12]  Michiel Steyaert,et al.  Monolithic Capacitive DC-DC Converter With Single Boundary–Multiphase Control and Voltage Domain Stacking in 90 nm CMOS , 2011, IEEE Journal of Solid-State Circuits.

[13]  Vincent Ng,et al.  A 92%-efficiency wide-input-voltage-range switched-capacitor DC-DC converter , 2012, 2012 IEEE International Solid-State Circuits Conference.

[14]  Stephen T. Kim,et al.  A 0.45–1V fully integrated reconfigurable switched capacitor step-down DC-DC converter with high density MIM capacitor in 22nm tri-gate CMOS , 2013, 2013 Symposium on VLSI Circuits.

[15]  Jaydeep Kulkarni,et al.  A 0.45–1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS , 2014, IEEE Journal of Solid-State Circuits.

[16]  Fabrice Paillet,et al.  FIVR — Fully integrated voltage regulators on 4th generation Intel® Core™ SoCs , 2014, 2014 IEEE Applied Power Electronics Conference and Exposition - APEC 2014.

[17]  C. Auth,et al.  A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors , 2012, 2012 Symposium on VLSI Technology (VLSIT).