Performance Analysis of GDI Based 1-bit Full Adder Circuit for Low Power & High Speed Applications

As technology scales into the nanometer regime power, delay and area plays a vital role for the analysis and design of various arithmetic logic circuits. Most of the low power and battery power VLSI applications, such as digital signal processing, image processing, video processing and microprocessors, extensively uses arithmetic operations. Binary addition considered as the most important part of the arithmetic unit because all other arithmetic operations usually involve addition. That’s why, analysis of low-power and high performance adder cells are of great interest and any modifications made to the full adder circuit would affect the entire system. Gate Diffusion Input (GDI) is one of the advanced technique in the field of low power digital IC design. This technique is used to reduce power consumption, delay and number of transistors count as compared to convectional CMOS design. This paper presents a detail performance analysis of GDI Based 1-bit Full Adder Circuit for Low Power Applications. Behaviour of the circuit based on average power and delay in nanometer regime has been analyzed and presented, so that it can be used for low power applications. All simulations results are based on BPTM model & have been carried out by Tanner EDA tool on 180nm, 90nm, 65nm and 45nm technology.

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