Energy efficient software through dynamic voltage scheduling

The energy usage of computer systems is becoming important, especially for portable battery-operated applications and embedded systems. A significant reduction in the energy consumption of a program can be achieved via code optimizations that transform the code to take advantage of the Instruction Set Architecture (ISA) of the target processor. These code optimizations result in significantly shorter execution times of the software which in turn allow the operating frequency of the processor to be reduced, while maintaining the same throughput as the conventionally coded application. This reduction in operating frequency allows dynamic voltage scheduling to be applied to the processor, which results in energy reduction. This work describes how the operating frequency and the supply voltage can be changed on a low power microprocessor. The examples used show that over an order of magnitude reduction in the energy consumption is possible by using the aforementioned techniques.

[1]  Anantha Chandrakasan,et al.  Embedded power supply for low-power DSP , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Manuel Blum,et al.  A Simple Unpredictable Pseudo-Random Number Generator , 1986, SIAM J. Comput..

[3]  Hal Wasserman,et al.  Comparing algorithm for dynamic speed-setting of a low-power CPU , 1995, MobiCom '95.

[4]  Scott Shenker,et al.  Scheduling for reduced CPU energy , 1994, OSDI '94.

[5]  Anantha P. Chandrakasan,et al.  Low-Power CMOS Design , 1997 .

[6]  Thomas D. Burd,et al.  The simulation and evaluation of dynamic voltage scaling algorithms , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[7]  Richard T. Witek,et al.  A 160 MHz 32 b 0.5 W CMOS RISC microprocessor , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.