Study of the impact of aging on many-core energy-efficient DSP systems

During the normal operational use, integrated circuits go through what is popularly known as wearout or aging. At system level, aging causes gradual speed degradation of the design over their service life. In a many-core homogeneous design and over a period of activity, this can lead to variation in speed depending on the workload distribution on cores. In the same design context, Voltage Scaling (VS) is another very widely used technique in gaining energy-efficiency. Process Variation (PV) also tend to have similar impact creating variation in speed and power among the cores. In this paper, we will first study the impact of aging and PV on above design system. Further, we will analyze their impact on energy efficient configurations under static and dynamic workload environment. Later, we will present our analysis over two different usage policies; using fastest core on the die as compared to uniform aging of all cores in the system. We conclude, that using fastest core in the system will yield higher performance benefits over its lifetime.

[1]  C.H. Kim,et al.  An Analytical Model for Negative Bias Temperature Instability , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[2]  David Blaauw,et al.  Analysis and mitigation of variability in subthreshold design , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[3]  Eiji Takeda,et al.  Hot-Carrier Effects in MOS Devices , 1995 .

[4]  D. Kwong,et al.  Dynamic NBTI of PMOS transistors and its impact on device lifetime , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[5]  Meeta Srivastav,et al.  Design of energy-efficient, adaptable throughput systems at near/sub-threshold voltage , 2013, TODE.

[6]  peixiong zhao,et al.  Physical mechanisms of negative-bias temperature instability , 2005 .

[7]  Souvik Mahapatra,et al.  Negative bias temperature instability in CMOS devices , 2005 .

[8]  Saurabh Dighe,et al.  Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor , 2011, IEEE Journal of Solid-State Circuits.

[9]  John M. Carulli,et al.  Impact of negative bias temperature instability on product parametric drift , 2004, 2004 International Conferce on Test.

[10]  Sani R. Nassif,et al.  High Performance CMOS Variability in the 65nm Regime and Beyond , 2007 .

[11]  Josep Torrellas,et al.  Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors , 2008, 2008 International Symposium on Computer Architecture.

[12]  David Blaauw,et al.  Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits , 2010, Proceedings of the IEEE.

[13]  Siddharth Garg,et al.  Cherry-picking: Exploiting process variations in dark-silicon homogeneous chip multi-processors , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[14]  Kaushik Roy,et al.  Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[15]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[16]  Josep Torrellas,et al.  The BubbleWrap many-core: Popping cores for sequential acceleration , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[17]  Sachin S. Sapatnekar,et al.  Impact of NBTI on SRAM read stability and design for reliability , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).