论文信息 - Hardness-by-design approach for 0.15 /spl mu/m fully depleted CMOS/SOI digital logic devices with enhanced SEU/SET immunity - 字舞流文

Hardness-by-design approach for 0.15 /spl mu/m fully depleted CMOS/SOI digital logic devices with enhanced SEU/SET immunity

S. Matsuda | S. Kuboyama | H. Shindou | A. Makihara | M. Midorikawa | T. Yamaguchi | Y. Iide | T. Yokose | Y. Tsuchiya | T. Arimitsu | H. Asai