Through-Silicon via Technology for 3D IC

Three-dimensional (3D) integration complements semiconductor scaling in enabling higher integration density as well as heterogeneous technology integration. Through 3D chip stacking it is possible to extend the number of functions per 3D chip well beyond the near-term capabilities of traditional scaling. The 3D strata may be realised using advanced CMOS technology nodes but may also exploit a wide variety of device technologies to optimise system performance. A key technology is the possibility for establishing electrical connections through the bulk of the silicon substrates on which semiconductor devices are realised. These connections are generally referred to as through-silicon-vias, or TSVs. A wide variety of technologies has been and continue be being proposed to realise such TSV connections. In this chapter, a classification of 3D technologies is proposed based on the system-level interconnect hierarchy. Different technology options for realising TSV structures are put forth and the main technological challenges discussed.