Experimental demonstration of strained Si nanowire GAA n-TFETs and inverter operation with complementary TFET logic at low supply voltages

Abstract In this work, strained Si (sSi) nanowire array of n-TFETs with gates all around (GAA) yielding ON-currents of 5 μA/μm at a supply voltage Vdd = 0.5 V are presented. Tilted ion implantation with BF2+ into NiSi2 dopant has been used to form a highly doped pocket for the source to channel tunneling junction. These devices indicate sub-threshold slopes (SS) below 60 mV/dec for Id

[1]  S. Trellenkamp,et al.  Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors , 2013, IEEE Electron Device Letters.

[2]  A. Ionescu,et al.  Understanding the Superlinear Onset of Tunnel-FET Output Characteristic , 2012, IEEE Electron Device Letters.

[3]  P. Fay,et al.  Perspectives of TFETs for low power analog ICs , 2012, 2012 IEEE Subthreshold Microelectronics Conference (SubVT).

[4]  K. K. Bourdelle,et al.  $\Omega$-Gated Silicon and Strained Silicon Nanowire Array Tunneling FETs , 2012, IEEE Electron Device Letters.

[5]  Saibal Mukhopadhyay,et al.  Exploring Tunnel-FET for ultra low power analog applications: A case study on operational transconductance amplifier , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[6]  Adrian M. Ionescu,et al.  Tunnel field-effect transistors as energy-efficient electronic switches , 2011, Nature.

[7]  A. Mallik,et al.  Tunnel Field-Effect Transistors for Analog/Mixed-Signal System-on-Chip Applications , 2012, IEEE Transactions on Electron Devices.

[8]  Qin Zhang,et al.  Low-Voltage Tunnel Transistors for Beyond CMOS Logic , 2010, Proceedings of the IEEE.

[9]  S. Mantl,et al.  An Improved Si Tunnel Field Effect Transistor With a Buried Strained $\hbox{Si}_{1-x}\hbox{Ge}_{x}$ Source , 2011, IEEE Electron Device Letters.

[10]  R. S. Gupta,et al.  Assessment of Ambipolar Behavior of a Tunnel FET and Influence of Structural Modifications , 2012 .

[11]  S. Trellenkamp,et al.  Demonstration of improved transient response of inverters with steep slope strained Si NW TFETs by reduction of TAT with pulsed I-V and NW scaling , 2013, 2013 IEEE International Electron Devices Meeting.

[12]  Drain induced barrier thinning on TFETs with different source/drain engineering , 2014, 2014 29th Symposium on Microelectronics Technology and Devices (SBMicro).

[13]  A. Mallik,et al.  Drain-Dependence of Tunnel Field-Effect Transistor Characteristics: The Role of the Channel , 2011, IEEE Transactions on Electron Devices.

[14]  Sorin Cristoloveanu,et al.  Tunneling field-effect transistor with epitaxial junction in thin germanium-on-insulator , 2009 .

[15]  Luca Selmi,et al.  Experimental demonstration of improved analog device performance in GAA-NW-TFETs , 2014, 2014 44th European Solid State Device Research Conference (ESSDERC).

[16]  K. Banerjee,et al.  Proposal for tunnel-field-effect-transistor as ultra-sensitive and label-free biosensors , 2012 .

[17]  G. Dewey,et al.  Fabrication, characterization, and physics of III–V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing , 2011, 2011 International Electron Devices Meeting.

[18]  Denis Flandre,et al.  A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA , 1996, IEEE J. Solid State Circuits.

[19]  Kevin S. Jones,et al.  Effect of fluorine on the diffusion of boron in ion implanted Si , 1998 .

[20]  Christophe Delerue,et al.  Effects of strain on the carrier mobility in silicon nanowires. , 2012, Nano letters.