Dynamic Reconfiguration Optimisation with Streaming Data Decompression

This paper presents a high performance reconfiguration controller enhanced with the use of streaming lossless decompression in its data path. Two reconfiguration controllers are designed, the first is a generic controller that utilises standard concepts such as Direct Memory Access, burst mode transfer of data and interrupts to maximise throughput. This controller is then improved by the inclusion of a streaming decompression engine optimised for the Internal Configuration Access Port (ICAP) interface. This new controller significantly improves the reconfiguration speed of the system and throughputs of up to 385 Mbytes/sec are recorded. As power and energy become very important constraints in the system design, an investigation of the overheads associated with the use of the reconfiguration controller are experimentally quantified and presented.

[1]  Walter Stechele,et al.  Using Partial-Run-Time Reconfigurable Hardware to accelerate Video Processing in Driver Assistance System , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[2]  Bin Zhang,et al.  A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[3]  Eric McDonald Runtime FPGA Partial Reconfiguration , 2008, 2008 IEEE Aerospace Conference.

[4]  A. Yurdakul,et al.  Dynamic Partial Self-Reconfiguration on Spartan-III FPGAs via a Parallel Configuration Access Port ( PCAP ) , 2008 .

[5]  Jose L Nunez-Yanez,et al.  Gigabyte per second streaming lossless data compression hardware based on a configurable variable-geometry CAM dictionary , 2006 .

[6]  Vassilios A. Chouliaras,et al.  A configurable and programmable motion estimation processor for the H.264 video codec , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[7]  Axel Jantsch,et al.  Run-time Partial Reconfiguration speed investigation and architectural design space exploration , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[8]  Jürgen Teich,et al.  Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration , 2004, IEEE International Parallel and Distributed Processing Symposium.

[9]  Mohammad Hosseinabady,et al.  Fault-tolerant dynamically reconfigurable NoC-based SoC , 2008, 2008 International Conference on Application-Specific Systems, Architectures and Processors.