Elixir: A new bandwidth-constrained mapping for Networks-on-chip

Nowadays, with technology shrinking and the huge demand for supporting multiple applications has led designers to use multiple IP cores within a single chip. Therefore, the designers have proposed Networks-on-chip to overcome the problems of future complex systems. Mapping IPs directly affects NoC design parameters such as latency and power consumption. In this paper we present a power and performance aware mapping technique based on the combination of both the bandwidth-constrained and branch and bound concepts. Results have shown improvements of the latency and power consumption of our technique when compared to other popular NoC mappings.

[1]  Ahmad Khademzadeh,et al.  Onyx: A new heuristic bandwidth-constrained mapping of cores onto tile-based Network on Chip , 2009, IEICE Electron. Express.

[2]  Norman P. Jouppi,et al.  Cacti 3. 0: an integrated cache timing, power, and area model , 2001 .

[3]  William J. Dally,et al.  A delay model and speculative architecture for pipelined routers , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[4]  An-Yeu Wu,et al.  A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[5]  Natalie D. Enright Jerger,et al.  Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Srinivasan Murali,et al.  Bandwidth-constrained mapping of cores onto NoC architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[7]  Li-Shiuan Peh,et al.  High-level power analysis for on-chip networks , 2004, CASES '04.

[8]  Radu Marculescu,et al.  Contention-aware application mapping for Network-on-Chip communication architectures , 2008, 2008 IEEE International Conference on Computer Design.

[9]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[10]  Radu Marculescu,et al.  Energy-aware mapping for tile-based NoC architectures under performance constraints , 2003, ASP-DAC '03.

[11]  Li-Shiuan Peh,et al.  A Statistical Traffic Model for On-Chip Interconnection Networks , 2006, 14th IEEE International Symposium on Modeling, Analysis, and Simulation.

[12]  Sharad Malik,et al.  Orion: a power-performance simulator for interconnection networks , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..

[13]  Li-Shiuan Peh,et al.  Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.