Transient faults in DRAMs: concept, analysis and impact on tests

Memory fault models have always been considered not to change with time. Therefore, tests constructed to detect sensitized faults need not take into consideration the time period between sensitizing and detecting the fault. In this paper; a new class of memory fault models is presented, where the time between sensitizing and detection should be considered. The paper also presents fault analysis results, based on defect injection and simulation, where transient faults have been observed. The impact of transient faults on testing is discussed and new detection conditions, in combination with a test, are given.

[1]  John L. Wyatt,et al.  Mismatch sensitivity of a simultaneously latched CMOS sense amplifier , 1991 .

[2]  Ad J. van de Goor,et al.  Impact of memory cell array bridges on the faulty behavior in embedded DRAMs , 2000, Proceedings of the Ninth Asian Test Symposium.

[3]  W. Gosney,et al.  A numerical analysis of the storage times of dynamic random-access memory cells incorporating ultrathin dielectrics , 1998 .

[4]  Frans P. M. Beenker,et al.  A realistic fault model and test algorithms for static random access memories , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  John K. DeBrosse,et al.  The evolution of IBM CMOS DRAM technology , 1995, IBM J. Res. Dev..

[6]  J Dietl,et al.  Buried stacked capacitor cells for 16M and 64M DRAMS , 1990, ESSDERC '90: 20th European Solid State Device Research Conference.

[7]  T. Kanarsky,et al.  Data Retention in SOI-DRAM with Trench Capacitor Cell , 1998, 28th European Solid-State Device Research Conference.

[8]  Zaid Al-Ars,et al.  Functional memory faults: a formal notation and a taxonomy , 2000, Proceedings 18th IEEE VLSI Test Symposium.