Time interleaved analog to digital converters: Tutorial 44
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[1] Robert K. Henderson,et al. A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit Highly Time-Interleaved Counter ADC with Low Power Comparator Design , 2013, IEEE Journal of Solid-State Circuits.
[2] Yu Lin,et al. An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[3] David B. Chester,et al. Simulink modeling of analog to digital converters for post conversion correction development and evaluation , 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).
[4] Borivoje Nikolic,et al. A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS , 2013, IEEE Journal of Solid-State Circuits.
[5] Zhiwei Xu,et al. A 40-mW 7-bit 2.2-GS/s Time-Interleaved Subranging CMOS ADC for Low-Power Gigabit Wireless Communications , 2012, IEEE Journal of Solid-State Circuits.
[6] Gernot Kubin,et al. Modeling, Identication, and Compensation of Channel Mismatch Errors in Time-Interleaved Analog-to-Digital Converters , 2005 .
[7] Changqing Feng,et al. A 1.6-Gsps High-Resolution Waveform Digitizer Based on a Time-Interleaved Technique , 2013, IEEE Transactions on Nuclear Science.
[8] Joel Goodman,et al. Polyphase Nonlinear Equalization of Time-Interleaved Analog-to-Digital Converters , 2009, IEEE Journal of Selected Topics in Signal Processing.
[9] Marinette Besson,et al. A 40GS/s 6b ADC in 65nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[10] Fang Xu. Perfect data reconstruction algorithm of time interleaved ADCs , 2006, 2006 IEEE International Test Conference.
[12] Claudio Nani,et al. A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS , 2011, IEEE Journal of Solid-State Circuits.
[13] Håkan Johansson,et al. A Polynomial-Based Time-Varying Filter Structure for the Compensation of Frequency-Response Mismatch Errors in Time-Interleaved ADCs , 2009, IEEE Journal of Selected Topics in Signal Processing.
[14] Xiaofei Chen,et al. A novel PR channelizer-based architecture for estimation and correction of timing and gain mismatches in two channel TI-ADCs , 2012, 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS).
[15] Patrick Satarzadeh,et al. A parametric polyphase domain approach to blind calibration of timing mismatches for M-channel time-interleaved ADCs , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.
[16] Matthew Martin,et al. A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[17] Alan V. Oppenheim,et al. Quantization and Compensation in Sampled Interleaved Multichannel Systems , 2010, IEEE Transactions on Signal Processing.
[18] David B. Chester,et al. Modeling of jitter and its effects on time interleaved ADC conversion , 2011, 2011 IEEE AUTOTESTCON.
[19] W. Black,et al. Time interleaved converter arrays , 1980, 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[20] Patrick Satarzadeh,et al. Digital Calibration of a Nonlinear S/H , 2009, IEEE Journal of Selected Topics in Signal Processing.
[21] Ieee Std,et al. IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters , 2011 .
[22] Chun-Cheng Huang,et al. A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques , 2011, IEEE Journal of Solid-State Circuits.
[23] Fan Ye,et al. A 14-bit 200-MS/s time-interleaved ADC calibrated with LMS-FIR and interpolation filter , 2011, 2011 IEEE International Conference of Electron Devices and Solid-State Circuits.
[24] U. Madhow,et al. Comprehensive digital correction of mismatch errors for a 400-msamples/s 80-dB SFDR time-interleaved analog-to-digital converter , 2005, IEEE Transactions on Microwave Theory and Techniques.