Work-function engineering in gate first technology for multi-VT dual-gate FDSOI CMOS on UTBOX

For the first time, we demonstrate low-V<inf>T</inf> (V<inf>Tlin</inf> ±0.32V) nMOS and pMOS adjusted in a gate first FDSOI technology by work-function engineering of TiN/TaAlN metal gates. Especially, for low-V<inf>T</inf> pMOS, various Chemical-Vapor-Deposited TaAlN stacks with optimized Al concentration have been studied to finely tune the work-function above midgap while maintaining good reliability and mobility. Short channel performance of 500µA/µm I<inf>ON</inf> and 245µA/µm I<inf>EFF</inf> at 2nA/µm I<inf>OFF</inf> and V<inf>DD</inf>=0.9V is reported on pMOS with a TaAlN gate. In addition, it is found that the combination of these two metal gates with either n- or p-doped ground planes below the Ultra-Thin Buried Oxide (BOX) can offer 4 different V<inf>T</inf> from 0.32V to 0.6V for both nMOS and pMOS, demonstrating a real multiple-V<inf>T</inf> capability for FDSOI CMOS while keeping the channel undoped and the V<inf>T</inf> variability around A<inf>VT</inf>=1.3mV.µm.