An on-chip double-bit error-correcting code for three-dimensional dynamic random-access memory

An error-correcting code is described which can correct up to two soft errors on each work line within a DRAM (dynamic random-access memory) chip. Three dimensional DRAM chips with trench-type capacitors are vulnerable to double-bit soft errors when an alpha particle strikes at the intervening space between two vertical capacitors setting off a plasma discharge between them. The author presents a systematic study of soft-error related problems, and discusses the methodologies to correct the double-bit memory-cells upsets by using on-chip ECC (error-correcting code) circuits. A comprehensive study is made to estimate the improvement in soft-error rate (SER) and mean time between failure (MTBF) by the proposed ECC technique. The ability of the circuit to correct soft errors in the presence of multiple-bit errors has also been analyzed using combinational enumeration.<<ETX>>

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