Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

The use of static random access memory (SRAM)-based field programmable gate arrays (FPGAs) in harsh radiation environments has grown in recent years. These types of programmable devices require special mitigation techniques targeting the configuration memory, the user logic, and the embedded RAM blocks. This article provides a comprehensive survey of the literature published in this rich research field during the past 10 years. Furthermore, it can also serve as a tutorial for space engineers, scientists, and decision makers who need an introduction to this topic.

[1]  Michael J. Wirthlin,et al.  Estimating TMR Reliability on FPGAs Using Markov Models , 2008 .

[2]  M. Caffrey,et al.  A review of Xilinx FPGA architectural reliability concerns from Virtex to Virtex-5 , 2007, 2007 9th European Conference on Radiation and Its Effects on Components and Systems.

[3]  Alan D. George,et al.  Reconfigurable Fault Tolerance: A Comprehensive Framework for Reliable and Adaptive FPGA-Based Space Computing , 2012, TRETS.

[4]  Joshua D. Snodgrass Low-Power Fault Tolerance for Spacecraft FPGA-Based Numerical Computing , 2006 .

[5]  Gary Swift,et al.  VIRTEX-4 VQ static SEU Characterization Summary , 2008 .

[6]  Khaled Benkrid,et al.  A novel high-performance fault-tolerant ICAP controller , 2012, 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

[7]  Gregory Allen Virtex-4VQ dynamic and mitigated single event upset characterization summary , 2009 .

[8]  M. Wirthlin,et al.  SEU-induced persistent error propagation in FPGAs , 2005, IEEE Transactions on Nuclear Science.

[9]  Mehdi Baradaran Tahoori,et al.  Soft error mitigation for SRAM-based FPGAs , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[10]  Charles D. Norton,et al.  An evaluation of the Xilinx Virtex-4 FPGA for on-board processing in an advanced imaging system , 2009, 2009 IEEE Aerospace conference.

[11]  C. Carmichael,et al.  Static Upset Characteristics of the 90nm Virtex-4QV FPGAs , 2008, 2008 IEEE Radiation Effects Data Workshop.

[12]  Tughrul Arslan,et al.  Methods and Mechanisms for Hardware Multitasking: Executing and Synchronizing Fully Relocatable Hardware Tasks in Xilinx FPGAs , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

[13]  M. Lopez-Vallejo,et al.  Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers , 2013, IEEE Transactions on Nuclear Science.

[14]  P. Adell Assessing and Mitigating Radiation Effects in Xilinx FPGAs , 2008 .

[15]  Herschel H. Loomis,et al.  Employment of Reduced Precision Redundancy for Fault Tolerant FPGA Applications , 2009, 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines.

[16]  P. Dodd,et al.  Production and propagation of single-event transients in high-speed digital logic ICs , 2004, IEEE Transactions on Nuclear Science.

[17]  J.N. Tombs,et al.  Selective Protection Analysis Using a SEU Emulator: Testing Protocol and Case Study Over the Leon2 Processor , 2007, IEEE Transactions on Nuclear Science.

[18]  Mehdi Baradaran Tahoori,et al.  Protecting SRAM-based FPGAs against multiple bit upsets using erasure codes , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[19]  Niccolò Battezzati,et al.  A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[20]  Brent Nelson,et al.  Using statistical models with duplication and compare for reduced cost FPGA reliability , 2010, 2010 IEEE Aerospace Conference.

[21]  L. Sterpone,et al.  RoRA: a reliability-oriented place and route algorithm for SRAM-based FPGAs , 2005, Research in Microelectronics and Electronics, 2005 PhD.

[22]  Luigi Carro,et al.  On the optimal design of triple modular redundancy logic for SRAM-based FPGAs , 2005, Design, Automation and Test in Europe.

[23]  Sandi Habinc,et al.  AMBA to SoCWire network on Chip bridge as a backbone for a Dynamic Reconfigurable Processing unit , 2011, 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

[24]  C. Poivey,et al.  Radiation assurance for the space environment , 2004, 2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866).

[25]  Harald Michalik,et al.  Enhancements of reconfigurable System-on-Chip Data Processing Units for Space Application , 2007, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).

[26]  Fernanda Gusmão de Lima Kastensmidt,et al.  Evaluating large grain TMR and selective partial reconfiguration for soft error mitigation in SRAM-based FPGAs , 2009, 2009 15th IEEE International On-Line Testing Symposium.

[27]  Florian Dittmann,et al.  A scalable platform for run-time reconfigurable satellite payload processing , 2012, 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

[28]  Suitability of reprogrammable FPGAs in space applications , 2002 .

[29]  G.M. Swift,et al.  Upset Characterization and Test Methodology of the PowerPC405 Hard-Core Processor Embedded in Xilinx Field Programmable Gate Arrays , 2007, 2007 IEEE Radiation Effects Data Workshop.

[30]  Massimo Violante,et al.  Efficient estimation of SEU effects in SRAM-based FPGAs , 2005, 11th IEEE International On-Line Testing Symposium.

[31]  Andrew Holmes-Siedle,et al.  Handbook of Radiation Effects , 1993 .

[32]  Chiara Sandionigi,et al.  A Novel Design Methodology for Implementing Reliability-Aware Systems on SRAM-Based FPGAs , 2011, IEEE Transactions on Computers.

[33]  Zdenek Kotásek,et al.  Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA , 2012, 2012 15th Euromicro Conference on Digital System Design.

[34]  Jürgen Becker,et al.  Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration , 2006, First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06).

[35]  共立出版株式会社 コンピュータ・サイエンス : ACM computing surveys , 1978 .

[36]  G. C. Messenger,et al.  The effects of radiation on electronic systems , 1986 .

[37]  A. Lesea,et al.  Effectiveness of Internal Versus External SEU Scrubbing Mitigation Strategies in a Xilinx FPGA: Design, Test, and Analysis , 2008, IEEE Transactions on Nuclear Science.

[38]  Massimo Violante,et al.  A new reliability-oriented place and route algorithm for SRAM-based FPGAs , 2006, IEEE Transactions on Computers.

[39]  Herschel H. Loomis,et al.  Reduced Precision Redundancy in a Radix-4 FFT implementation on a Field Programmable Gate Array , 2011, 2011 Aerospace Conference.

[40]  K. Chapman SEU Strategies for Virtex-5 Devices , 2010 .

[41]  Paula J. Pingree,et al.  Advancing NASA's on-board processing capabilities with reconfigurable FPGA technologies: Opportunities & implications , 2010, 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW).

[42]  H E NEWELL,et al.  The space environment. , 1960, Science.

[43]  Mihalis Psarakis,et al.  A soft error vulnerability analysis framework for Xilinx FPGAs , 2014, FPGA.

[44]  J.M. Mogollon,et al.  FTUNSHADES2: A novel platform for early evaluation of robustness against SEE , 2011, 2011 12th European Conference on Radiation and Its Effects on Components and Systems.

[45]  J. Johnson,et al.  Using Duplication with Compare for On-line Error Detection in FPGA-based Designs , 2008, 2008 IEEE Aerospace Conference.

[46]  M. Wirthlin,et al.  Fine-Grain SEU Mitigation for FPGAs Using Partial TMR , 2008, IEEE Transactions on Nuclear Science.

[47]  Ann Gordon-Ross,et al.  Partially reconfigurable system-on-chips for adaptive fault tolerance , 2011, 2011 International Conference on Field-Programmable Technology.

[48]  L. Sterpone,et al.  A New Algorithm for the Analysis of the MCUs Sensitiveness of TMR Architectures in SRAM-Based FPGAs , 2008, IEEE Transactions on Nuclear Science.

[49]  Alan D. George,et al.  Acceleration of FPGA Fault Injection Through Multi-Bit Testing , 2010, ERSA.

[50]  M. Caffrey,et al.  Domain Crossing Errors: Limitations on Single Device Triple-Modular Redundancy Circuits in Xilinx FPGAs , 2007, IEEE Transactions on Nuclear Science.

[51]  Sandi Habinc,et al.  Dynamic Partial Reconfiguration in Space Applications , 2009, 2009 NASA/ESA Conference on Adaptive Hardware and Systems.

[52]  Alan D. George,et al.  Overhead and reliability analysis of algorithm-based fault tolerance in FPGA systems , 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

[53]  Zdenek Kotásek,et al.  Test platform for fault tolerant systems design properties verification , 2012, 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

[54]  Gabriel L. Nazar,et al.  Accelerated FPGA repair through shifted scrubbing , 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

[55]  Martin Straka,et al.  Generic partial dynamic reconfiguration controller for fault tolerant designs based on FPGA , 2010, NORCHIP 2010.

[56]  Mikel Azkarate-askasua,et al.  ATB: Area-Time response Balancing algorithm for scheduling real-time hardware tasks , 2010, 2010 International Conference on Field-Programmable Technology.

[57]  Niccolò Battezzati,et al.  A Novel Design Flow for the Performance Optimization of Fault Tolerant Circuits on SRAM-based FPGA's , 2008, 2008 NASA/ESA Conference on Adaptive Hardware and Systems.

[58]  Mikel Azkarate-askasua,et al.  A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[59]  Iouliia Skliarova Self-correction of FPGA-Based Control Units , 2005, ICESS.

[60]  Michael J. Wirthlin,et al.  FPGA partial reconfiguration via configuration scrubbing , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[61]  D.L. McMurtrey,et al.  A Comparison of TMR With Alternative Fault-Tolerant Design Techniques for FPGAs , 2007, IEEE Transactions on Nuclear Science.

[62]  Mihalis Psarakis,et al.  Scrubbing-based SEU mitigation approach for Systems-on-Programmable-Chips , 2011, 2011 International Conference on Field-Programmable Technology.

[63]  J. Tombs,et al.  A non-invasive system for the measurement of the robustness of microprocessor-type architectures against radiation-induced soft errors , 2008, 2008 IEEE Instrumentation and Measurement Technology Conference.

[64]  M. Wirthlin,et al.  Fault Tolerant ICAP Controller for High-Reliable Internal Scrubbing , 2008, 2008 IEEE Aerospace Conference.

[65]  Michael J. Wirthlin,et al.  A Comparison of fault-tolerant memories in SRAM-based FPGAs , 2010, 2010 IEEE Aerospace Conference.

[66]  L Sterpone,et al.  Robustness analysis of soft error accumulation in SRAM-FPGAs using FLIPPER and STAR/RoRA , 2008, 2008 European Conference on Radiation and Its Effects on Components and Systems.

[67]  Chen Wei Tseng,et al.  SEU-Susceptibility of Logical Constants in Xilinx FPGA Designs , 2009, IEEE Transactions on Nuclear Science.

[68]  Margaret A. Sullivan Reduced precision redundancy applied to arithmetic operations in field programmable gate arrays for satellite control and sensor systems , 2008 .

[69]  Soft Error Mitigation Using Prioritized Essential Bits , 2012 .

[70]  Tughrul Arslan,et al.  Snake: An Efficient Strategy for the Reuse of Circuitry and Partial Computation Results in High-Performance Reconfigurable Computing , 2011, 2011 International Conference on Reconfigurable Computing and FPGAs.

[71]  Marco Lanuzza,et al.  Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications , 2010, TRETS.

[72]  Tanya Vladimirova,et al.  Adaptive FDIR framework for payload data processing systems using reconfigurable FPGAs , 2013, 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013).

[73]  Tughrul Arslan,et al.  An FPGA task allocator with preliminary First-Fit 2D packing algorithms , 2011, 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

[74]  Michael J. Wirthlin,et al.  Reduced-Precision Redundancy on FPGAs , 2011, Int. J. Reconfigurable Comput..

[75]  M. Caffrey,et al.  On-Orbit Results for the Xilinx Virtex-4 FPGA , 2012, 2012 IEEE Radiation Effects Data Workshop.

[76]  M.A. Aguirre,et al.  A New Approach to Estimate the Effect of Single Event Transients in Complex Circuits , 2007, IEEE Transactions on Nuclear Science.

[77]  Sergio D'Angelo,et al.  Evaluation of Single Event Upset Mitigation Schemes for SRAM based FPGAs using the FLIPPER Fault Injection Platform , 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

[78]  Harald Michalik,et al.  The SoCWire protocol (SoCP): A flexible and minimal protocol for a Network-on-Chip , 2012, 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

[79]  J R Azambuja,et al.  Mitigating soft errors in SRAM-based FPGAs by using large grain TMR with selective partial reconfiguration , 2008, 2008 European Conference on Radiation and Its Effects on Components and Systems.

[80]  Massimo Violante,et al.  Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs , 2007, 12th IEEE European Test Symposium (ETS'07).

[81]  M. Wirthlin,et al.  Improving FPGA Design Robustness with Partial TMR , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[82]  M. Caffrey,et al.  Static Proton and Heavy Ion Testing of the Xilinx Virtex-5 Device , 2007, 2007 IEEE Radiation Effects Data Workshop.

[83]  Jacob A. Abraham,et al.  Algorithm-Based Fault Tolerance for Matrix Operations , 1984, IEEE Transactions on Computers.

[84]  Gary R. Burke,et al.  Fault Tolerant State Machines , 2004 .

[85]  Harald Michalik,et al.  SoCWire: A Network-on-Chip Approach for Reconfigurable System-on-Chip Designs in Space Applications , 2008, 2008 NASA/ESA Conference on Adaptive Hardware and Systems.

[86]  David Merodio Codinachs,et al.  Experimental Validation of Fault Injection Analyses by the FLIPPER Tool , 2010, IEEE Transactions on Nuclear Science.

[87]  P. Graham,et al.  Radiation-induced multi-bit upsets in SRAM-based FPGAs , 2005, IEEE Transactions on Nuclear Science.

[88]  G Allen,et al.  Assessing and mitigating radiation effects in Xilinx SRAM FPGAs , 2008, 2008 European Conference on Radiation and Its Effects on Components and Systems.

[89]  Jürgen Becker,et al.  Dynamic and Partial FPGA Exploitation , 2007, Proceedings of the IEEE.

[90]  Zdenek Kotásek,et al.  Checker Design for On-line Testing of Xilinx FPGA Communication Protocols , 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

[91]  Michael Rice,et al.  Reduced-Precision Redundancy for Reliable FPGA Communications Systems in High-Radiation Environments , 2013, IEEE Transactions on Aerospace and Electronic Systems.

[92]  Harald Michalik,et al.  Architecture verification of the SoCWire NoC approach for safe dynamic partial reconfiguration in space applications , 2010, 2010 NASA/ESA Conference on Adaptive Hardware and Systems.

[93]  Massimo Violante,et al.  Multiple errors produced by single upsets in FPGA configuration memory: a possible solution , 2005, European Test Symposium (ETS'05).

[94]  Roger Boada Gardenyes Trends and patterns in ASIC and FPGA use in space missions and impact in technology roadmaps of the European Space Agency , 2011 .

[95]  Mikel Azkarate-askasua,et al.  R3TOS: A reliable reconfigurable real-time operating system , 2010, 2010 NASA/ESA Conference on Adaptive Hardware and Systems.

[96]  Ali Akoglu,et al.  SCARS: Scalable Self-Configurable Architecture for Reusable Space Systems , 2008, 2008 NASA/ESA Conference on Adaptive Hardware and Systems.

[97]  J. Napoles,et al.  A Complete Emulation System for Single Event Effects Analysis , 2008, 2008 4th Southern Conference on Programmable Logic.

[98]  Brent E. Nelson,et al.  RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

[99]  Fabio Margaglia,et al.  Analysis of SEU effects in partially reconfigurable SoPCs , 2011, 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

[100]  Wayne Luk,et al.  Design Optimizations for Tiled Partially Reconfigurable Systems , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[101]  Heather M. Quinn,et al.  A Test Methodology for Determining Space Readiness of Xilinx SRAM-Based FPGA Devices and Designs , 2009, IEEE Transactions on Instrumentation and Measurement.

[102]  Martin Straka,et al.  Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration , 2010, DSD 2010.