Noise Immune Convolutional Encoder Design and Its Implementation in Tanner

With the rapid advances in integrated circuit(IC) technologies, number of functions on a chip was increasing at a very fast rate, with which interconnect density is increasing especially in functional logic chips. The on-chip noise affects are increasing and needs to be addressed. In this paper we have implemented a convolution encoder using a technique that provides higher noise immunity. The encoder circuit is simulated in Tanner 15.0 with data rate of 25Mbps and a clock frequency of 250MHz