Design and Implementation of a Hardware Divider in Finite Field

An FPGA based implementation of divider in primary field i.e. GF(p) is presented. The algorithm implemented is based on hardware adapted unified modular division for both integer and Montgomery domain. This algorithm can also determine the inverse of an element in GF(p) when dividend is 1. The computational complexity has been reduced to using only additions, bit shifts and a simple control flow. The FPGA implementation of this design occupies only 15 registers and 6 adders with negligible overheads. The design can operate at over 80 MHz on Xilinx-XST™ Spartan device. It has been captured and synthesized using contemporary design flow and can be ported to any ASIC or PLD platform.