A Smart Frame Buffer

Using a RISC processor to drive a simple frame buffer yields good 2D color graphics performance. But processor, memory, and bus architectures can prevent processors from saturating video RAM bandwidth. The smart frame buffer is a small cheap gate array that makes full memory bandwidth available to the CPU by expanding 32 data bits into operations upon 32 pixels; pixels can be 8, 16, or 32 bits deep. We avoid the cost and complexity of typical graphics accelerators by leaving high-level control to the CPU, yet achieve comparable performance. This paper describes the architecture of the smart frame buffer chip, sketches several software algorithms for common X11 graphics operations, and compares performance against other popular graphics hardware.

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