VARIATION-TOLERANT SUB-THRESHOLD SRAM CELL DESIGN TECHNIQUE

At present SRAM cell is under renovation stage. Researchers are trying to propose an SRAM cell that withstands the ever-increasing PVT (process, voltage and temperature) variations and supports low-voltage operation even under subthreshold regime. In this article, a 10T SRAM cell based on DSBB and DTMOS techniques is proposed. This cell is identical to conventional 10T (CON10T) SRAM cell except the body bias connections of the FETs used in the design. This cell is operated in subthreshold region varying from 400 mV to 200 mV. The proposed cell offers 2.64× higher read current and 1.36× tighter spread in read current. It takes 38.04% shorter time to sense a particular data available at the storage nodes with 50.58% improvement in its distribution. The proposed cell benefits 19.48% of write delay and 3.33× tighter spread in write delay compared with its conventional counterpart. It also offers 2× improvement in its write-ability and 2.67× increment in read current to leakage current ratio (IREAD/ILEAK) with same RSNM (105 mV) and hold power (1.17 nW) @ 400 mV.

[1]  Soumitra Pal,et al.  Comparative study of CMOS- and FinFET-based 10T SRAM cell in subthreshold regime , 2014, 2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies.

[2]  C. Radens,et al.  A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing , 2008, IEEE Journal of Solid-State Circuits.

[4]  A.P. Chandrakasan,et al.  A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy , 2008, IEEE Journal of Solid-State Circuits.

[5]  A.P. Chandrakasan,et al.  Nanometer MOSFET Variation in Minimum Energy Subthreshold Circuits , 2008, IEEE Transactions on Electron Devices.

[6]  Mohd. Hasan,et al.  A technique to mitigate impact of process, voltage and temperature variations on design metrics of SRAM Cell , 2012, Microelectron. Reliab..

[7]  Jason Liu,et al.  A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[8]  Tughrul Arslan,et al.  Variation resilient subthreshold SRAM cell design technique , 2012 .

[9]  Kaushik Roy,et al.  Robust ultra-low power sub-threshold DTMOS logic , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[10]  R.H. Dennard,et al.  An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches , 2008, IEEE Journal of Solid-State Circuits.

[11]  Kaushik Roy,et al.  Ultra-low power digital subthreshold logic circuits , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[12]  Mohammad Sharifkhani,et al.  A Subthreshold Symmetric SRAM Cell With High Read Stability , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[13]  Soumitra Pal,et al.  Stability and variability enhancement of 9T SRAM cell for subthreshold operation , 2014, 2014 Annual IEEE India Conference (INDICON).

[14]  Kaushik Roy,et al.  A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[15]  S. Shimada,et al.  Low-power embedded SRAM modules with expanded margins for writing , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..