Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods
暂无分享,去创建一个
[1] Eric Beyne,et al. Impact of 3D design choices on manufacturing cost , 2009, 2009 IEEE International Conference on 3D System Integration.
[2] Jae-Hyun Park,et al. The electrical, mechanical properties of through-silicon-via insulation layer for 3D ICs , 2009, 2009 International Conference on Electronic Packaging Technology & High Density Packaging.
[3] Chenming Hu. BSIM model for circuit design using advanced technologies , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).
[4] B. Verlinden,et al. Electrical evaluation of 130-nm MOSFETs with TSV proximity in 3D-SIC structure , 2010, 2010 IEEE International Interconnect Technology Conference.
[5] So-Ra Kim,et al. 8Gb 3D DDR3 DRAM using through-silicon-via technology , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[6] John H. Lau,et al. TSV manufacturing yield and hidden costs for 3D IC integration , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).
[7] Young-Hyun Jun,et al. 8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology , 2009, IEEE Journal of Solid-State Circuits.
[8] P. Holmberg,et al. Automatic balancing of linear AC bridge circuits for capacitive sensor elements , 1994, Conference Proceedings. 10th Anniversary. IMTC/94. Advanced Technologies in I & M. 1994 IEEE Instrumentation and Measurement Technolgy Conference (Cat. No.94CH3424-9).
[9] Zhihong Huang,et al. Electromigration of Cu-Sn-Cu micropads in 3D interconnect , 2008, 2008 58th Electronic Components and Technology Conference.
[10] C. Sharbono,et al. Factors affecting copper filling process within high aspect ratio deep vias for 3D chip stacking , 2006, 56th Electronic Components and Technology Conference 2006.
[11] Bas M. Putter. On-chip RC measurement and calibration circuit using Wheatstone bridge , 2008, 2008 IEEE International Symposium on Circuits and Systems.
[12] Ding-Ming Kwai,et al. On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification , 2009, 2009 Asian Test Symposium.
[13] Hsien-Hsin S. Lee,et al. An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth , 2010, HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture.
[14] Taewhan Kim,et al. Clock tree synthesis with pre-bond testability for 3D stacked IC Designs , 2010, Design Automation Conference.
[15] Paul D. Franzon,et al. Through Silicon Via(TSV) defect/pinhole self test circuit for 3D-IC , 2009, 2009 IEEE International Conference on 3D System Integration.
[16] Paresh Limaye,et al. Design issues and considerations for low-cost 3D TSV IC technology , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[17] Luca Benini,et al. A low-overhead fault tolerance scheme for TSV-based 3D network on chip links , 2008, ICCAD 2008.
[18] H. Tu,et al. Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).
[19] Kumiko Nomura,et al. Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.
[20] Shinji Miyamoto,et al. Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories , 2009, 2009 IEEE International Conference on 3D System Integration.
[21] Yu Cao,et al. New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration , 2006, IEEE Transactions on Electron Devices.
[22] Luca Benini,et al. Design Issues and Considerations for Low-Cost 3-D TSV IC Technology , 2010, IEEE Journal of Solid-State Circuits.