Compression technique for interactive BIST application

This paper presents a compression technique that reduces the test data volume while achieving high fault coverage within a Built-In Self-Test environment. The LFSR control data target only the RPR faults. The data are further reduced using a new code. Analysis of essential attributes of the control data is performed to assess their effect on the compression technique. The scheme was applied to several benchmark cores and indicated a superior effect than previously used compression techniques.

[1]  Nur A. Touba,et al.  Altering a pseudo-random bit sequence for scan-based BIST , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[2]  Huaguo Liang,et al.  A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters , 2001, J. Electron. Test..

[3]  Abraham Lempel,et al.  Compression of individual sequences via variable-rate coding , 1978, IEEE Trans. Inf. Theory.

[4]  Nur A. Touba,et al.  Modifying user-defined logic for test access to embedded cores , 1997, Proceedings International Test Conference 1997.

[5]  C. E. SHANNON,et al.  A mathematical theory of communication , 1948, MOCO.

[6]  Benoit Nadeau-Dostie,et al.  A new procedure for weighted random built-in self-test , 1990, Proceedings. International Test Conference 1990.

[7]  Janusz Rajski,et al.  Decompression of test data using variable-length seed LFSRs , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[8]  D AgrawalVishwani,et al.  A Tutorial on Built-In Self-Test, Part 2 , 1993 .

[9]  Vishwani D. Agrawal,et al.  A Tutorial on Built-In Self-Test, Part 2: Applications , 1993, IEEE Des. Test Comput..

[10]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[11]  Bernard Courtois,et al.  Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers , 1995, IEEE Trans. Computers.

[12]  J. Li,et al.  Tree-structured linear cellular automata and their applications as PRPGs , 1997, Proceedings International Test Conference 1997.

[13]  J. Desposito.  SOC and deep-submicron technology drive new DFT strategies , 1998 .

[14]  Krishnendu Chakrabarty,et al.  Test data compression for system-on-a-chip using Golomb codes , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[15]  Nur A. Touba,et al.  Test vector decompression via cyclical scan chains and its application to testing core-based designs , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[16]  Dong Sam Ha,et al.  COMPACT: a hybrid method for compressing test data , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[17]  B. Koneman,et al.  LFSR-Coded Test Patterns for Scan Designs , 1993 .

[18]  S. Hellebrand,et al.  An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[19]  Dong Sam Ha,et al.  An efficient method for compressing test data , 1997, Proceedings International Test Conference 1997.

[20]  Bernard Courtois,et al.  Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers , 1992 .

[21]  Nur A. Touba,et al.  Scan vector compression/decompression using statistical coding , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[22]  Yervant Zorian,et al.  Introducing Core-Based System Design , 1997, IEEE Des. Test Comput..

[23]  Paul H. Bardell.  Analysis of cellular automata used as pseudorandom pattern generators , 1990, Proceedings. International Test Conference 1990.

[24]  Yervant Zorian.  Testing the monster chip , 1999 .

[25]  H. Wunderlich,et al.  Bit-flipping BIST , 1996, ICCAD 1996.

[26]  Gundolf Kiefer,et al.  Using BIST control for pattern generation , 1997, Proceedings International Test Conference 1997.