Fabrication and Assembly of Cu-RDL-Based 2.5-D Low-Cost Through Silicon Interposer (LC–TSI)

Two-and-a-half-dimensional integration enables high-density interdie connections with low cost. This paper presents a through silicon interposer (TSI) fabrication process and detailed characterization and measurement results of redistribution layers and through silicon vias for low-cost 2.5-D integration.

[1]  Chin-Li Kao,et al.  TSV technology for 2.5D IC solution , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[2]  H. Y. Chen,et al.  A high-performance low-cost chip-on-Wafer package with sub-μm pitch Cu RDL , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[3]  Eric Beyne,et al.  Si interposer build-up options and impact on 3D system cost , 2013, 2013 IEEE International 3D Systems Integration Conference (3DIC).

[4]  Zhe Li,et al.  Development of an optimized power delivery system for 3D IC integration with TSV silicon interposer , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[5]  W. Dehaene,et al.  Test structures for characterization of through silicon vias , 2010, 2010 International Conference on Microelectronic Test Structures (ICMTS).

[6]  Guruprasad Katti,et al.  The cost study of 300mm through silicon interposer (TSI) with BEOL interconnect , 2013, 2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013).