FPGA Design Framework for Dynamic Partial Reconfiguration

Recent advances in Xilinx’s FPGA devices and design tools significantly improve the practicality of incorporating dynamic partial reconfiguration into high-performance embedded computing systems. By taking advantage of internal configuration access ports, Xilinx FPGAs are capable of in-situ partial reconfiguration without the need for external components, a technique defined as self-reconfiguration. However, proper planning and a significant amount of manual floorplanning are required to effectively leverage partial reconfiguration and truly enhance the capabilities of a system and/or achieve cost savings. This paper proposes and analyzes partial reconfiguration design methodologies to enable selfreconfiguration using Virtex-4 and Virtex-5 FPGAs.