HVoC: a Hybrid Model Checking - Interactive Theorem Proving Approach for Functional Verification of Digital Circuits

[1]  Shobha Vasudevan,et al.  A Comparative Study of Assertion Mining Algorithms in GoldMine , 2019 .

[2]  David M. Russinoff.  Formal Verification of Floating-Point Hardware Design , 2018 .

[3]  Osman Hasan,et al.  Ver2Smv — A tool for automatic verilog to SMV translation for verifying digital circuits , 2018, 2018 International Conference on Engineering and Emerging Technologies (ICEET).

[4]  Osman Hasan,et al.  A Library for Combinational Circuit Verification Using the HOL Theorem Prover , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Ashok B. Mehta.  SystemVerilog Assertions (SVA) , 2018 .

[6]  Ashok B. Mehta.  ASIC/SoC Functional Design Verification , 2018 .

[7]  Thomas A. Henzinger,et al.  Handbook of Model Checking , 2018, Springer International Publishing.

[8]  Marly Roncken,et al.  A Framework for Asynchronous Circuit Modeling and Verification in ACL2 , 2017, Haifa Verification Conference.

[9]  Daniel G. Saab,et al.  Automatic Assertion Generation for Simulation, Formal Verification and Emulation , 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

[10]  Osman Hasan,et al.  A HOL Library for Hardware Verification using Theorem Proving , 2017 .

[11]  André Rossi,et al.  Formal Verification of Arithmetic Circuits by Function Extraction , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Rolf Drechsler,et al.  Precise error determination of approximated components in sequential circuits with model checking , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[13]  Prabhat Mishra,et al.  Scalable SoC trust verification using integrated theorem proving and model checking , 2016, 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[14]  Marco Roveri,et al.  Verilog2SMV: A tool for word-level verification , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[15]  Jesper Bengtson,et al.  Interactive Theorem Proving , 2021, Lecture Notes in Computer Science.

[16]  Stephan Merz,et al.  Interactive Theorem Proving , 2016, Lecture Notes in Computer Science.

[17]  Yvon Savaria,et al.  Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits , 2015, Microelectron. Reliab..

[18]  Sofiène Tahar,et al.  Formal Verification Methods , 2015 .

[19]  Peter-Michael Seidel.  A Case for Multi-level Combination of Theorem Proving and Model Checking Tools , 2014, 2014 15th International Microprocessor Test and Verification Workshop.

[20]  Johann Glaser,et al.  Yosys-A Free Verilog Synthesis Suite , 2013 .

[21]  Carlo A. Furia,et al.  User manual , 2023, International Transport Forum Policy Papers.