Performance analysis of output buffers in multistage interconnection networks with multiple paths

Multistage interconnection networks with multiple paths can support higher bandwidth than those of non-blocking networks by passing multiple packets to the same destination simultaneously. In the multiple path networks, the performance of the output buffer affects the whole system performance and is closely coupled with the output traffic distribution i.e. the packet arrival rate at each output link destined to a given output module. Many multiple path networks produce the nonuniform output traffic distribution even if the input traffic pattern is random and uniform. In this paper, performances of the output buffers for several multiple path networks are investigated by our proposed analysis model. It is shown that the output traffic distributions are different with the various multiple path networks and the output buffer performance such as packet loss probability and delay gets better as nonuniformity of the output traffic distribution becomes higher.

[1]  Samuel P. Morgan,et al.  Input Versus Output Queueing on a Space-Division Packet Switch , 1987, IEEE Trans. Commun..

[2]  Hyunsoo Yoon,et al.  Performance analysis of an ATM switch with multiple paths , 1995, Proceedings of International Conference on Network Protocols.

[3]  Achille Pattavina,et al.  Multistage shuffle networks with shortest path and deflection routing for high-performance ATM switching: the closed-loop shuffleout , 1994, IEEE Trans. Commun..

[4]  Alberto Leon-Garcia,et al.  A Self-Routing Multistage Switching Network for Broadband ISDN , 1990, IEEE J. Sel. Areas Commun..

[5]  J. Robert Heath,et al.  Classification Categories and Historical Development of Circuit Switching Topologies , 1983, CSUR.

[6]  R. Y. Awdeh,et al.  Design and performance analysis of an output-buffering ATM switch with complexity of O(Nlog/sub 2/N) , 1994, Proceedings of ICC/SUPERCOMM'94 - 1994 International Conference on Communications.

[7]  Fouad A. Tobagi,et al.  Architecture, Performance, and Implementation of the Tandem Banyan Fast Packet Switch , 1991, IEEE J. Sel. Areas Commun..

[8]  Marc Snir,et al.  The Performance of Multistage Interconnection Networks for Multiprocessors , 1983, IEEE Transactions on Computers.

[9]  Ted H. Szymanski,et al.  On the Permutation Capability of Multistage Interconnection Networks , 1987, IEEE Transactions on Computers.

[10]  Satoshi Nojima,et al.  Integrated Services Packet Network Using Bus Matrix Switch , 1987, IEEE J. Sel. Areas Commun..

[11]  Achille Pattavina,et al.  Multistage shuffle networks with shortest path and deflection routing for high performance ATM switching: the open-loop shuffleout , 1994, IEEE Trans. Commun..

[12]  Thomas G. Robertazzi,et al.  Input Versus Output Queueing on a SpaceDivision Packet Switch , 1993 .

[13]  Kyungsook Y. Lee,et al.  Performance Analysis of Multibuffered Packet-Switching Networks in Multiprocessor Systems , 1990, IEEE Trans. Computers.

[14]  Thomas G. Robertazzi Performance Analysis of Multibuffered PacketSwitching Networks in Multiprocessor Systems , 1993 .

[15]  Anthony S. Acampora,et al.  The Knockout Switch: A Simple, Modular Architecture for High-Performance Packet Switching , 1987, IEEE J. Sel. Areas Commun..