Managing Process Variation in Intel’s 45nm CMOS Technology

The key message of this paper is that process variation is not an insurmountable barrier to Moore’s Law, but is simply another challenge to be overcome. This message is illustrated with data from the 45nm process generation where process variation is shown to be at least equivalent to (and in many cases better than) process variation in the 65nmand 90nm-process generations. We begin this paper with an introduction and historical overview of process variation. Although there has been a trend in recent years to convey process variation as a new challenge associated with advanced CMOS technologies, process variation has been a continuing theme throughout the history of semiconductor process engineering. We continue with a review of critical sources of variation specific to the 45nm generation, including highly random effects (random dopant fluctuation, line-edge and linewidth roughness), variation associated with the gate dielectric (oxide thickness, fixed charge, defects and traps), patterning proximity effects (classical, and those based on optical proximity correction (OPC)), variation associated with polish (shallow-trench isolation, gate, and interconnect), variation associated with strain (wafer-level biaxial, high-stress capping layers, and embedded silicongermanium (SiGe)), and variation associated with implants and anneals (implant tool-based, implant profile, rapid-thermal anneal, and implant variation associated with poly-grain boundaries). We then explore the variety of process, design, and layout techniques used in the 45nm generation to mitigate the impact of variation. Pure process mitigation techniques include targeting key transistor properties to reduce random dopant fluctuation, reducing traps at the high-k metal-gate (HiK+MG) interface to reduce random charge variation, improving patterning techniques to reduce lineedge roughness and endcap variation, and improving polishing technologies to reduce systematic cross-wafer variation. Combination design-process techniques include optimizing topology, using OPC to reduce random and systematic variation, and adding dummy features to reduce systematic variation. Pure design techniques include chopping techniques to compensate for random variation and common-centroid layout techniques to compensate for systematic variation. We move on to illustrate the success of these mitigation techniques by reviewing detailed data characterizing variation in the 45nm generation. Three different types of measurements are presented to illustrate various variation mechanisms. The first is in-fab measurement of variation, used to characterize gate dimensional variation for the 45nm versus 65nm and 90nm generations. The second is low-frequency electrical measurement of matched transistor pairs, used to extract random variation for 45nm versus 65nm transistors. The third is measurements of product ring oscillators, used to determine both systematic and random within-wafer and within-die variation for 45nm versus 65nm products. Intel Technology Journal, Volume 12, Issue 2, 2008 Managing Process Variation in Intel’s 45nm CMOS Technology 94 Finally, we reinforce the key message that variation does not pose an insurmountable barrier to Moore’s law, but is simply another challenge to be overcome. INTRODUCTION AND HISTORICAL OVERVIEW Moore’s-Law-driven technology scaling has improved VLSI performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore’s Law, a variety of challenges will need to be overcome. One of these challenges is management of process variation [1, 2]. Although there has been a trend in the CMOS literature in recent years to convey process variation as a new challenge associated with advanced CMOS technologies, that viewpoint does not effectively capture the history of process variation. Process variation has always been a critical aspect of semiconductor fabrication. The first discussion of random variation in semiconductor devices was Shockley’s 1961 analysis of random fluctuations in junction breakdown [3]. Shockley’s concepts of random variation were extended to MOS devices by Keyes [4] in 1975 when he modeled the effect of random fluctuations in the number of impurity atoms in the depletion layer of a field-effect transistor (FET). Systematic variation in MOS devices was first addressed formally in 1974 by Schemmert and Zimmer [5] when they computed the sensitivity of ion-implanted MOS threshold voltages as a function of the implantation energy and the oxide thickness. A more extensive analysis of threshold voltage sensitivity using a closed-forum numerical simulation was presented by Yokoyama et al. in 1980 [6] with a Monte Carlo approach developed by Alvarez in the same year [7]. Interconnect variation has also received significant attention over the years, with Lin et al. presenting a detailed treatment in 1998 [8] that was expanded by many authors in the early 2000s [37, 40–43]. While the continued decrease in the ratio of feature sizes to fundamental dimensions (such as atomic dimensions and light wavelengths) means that management of variation will play a significant role in future technology scaling, the evidence shows that process variation has been a continuing theme throughout semiconductor history. CRITICAL SOURCES OF VARIATION IN THE 45NM GENERATION 45nm technology is subject to a number of variation effects that are well documented in the literature [9–63]. Examples include highly random effects (random dopant fluctuation (RDF) [9–17], line-edge and line-width roughness, line-edge and line-width roughness (LER) and (LWR), respectively [18–21]), variations in the gate dielectric (oxide thickness variations [22–26], fixed charge [27], and defects and traps [28–34]), patterning proximity effects (classical, and those associated with OPC [35]), variation associated with polish (shallow trench isolation (STI) [36, 40], gate [37–38], and interconnect [39,42-44]), variation associated with strain (wafer-level biaxial 46–49, 57], high-stress capping layers [50–52], and embedded silicon-germanium (SiGe) [53– 56]), and variation associated with implants and anneals (tool-based [58], pocket implants [59–60], rapid-thermal anneal RTA [61] and variation associated with poly grains [62–63]). Random Dopant Fluctuation (RDF) MOS threshold voltage variation due to random fluctuations in the number and location of dopant atoms is an increasingly significant effect in sub-micron CMOS technologies (see Figure 1 and [9–17]). As the number of dopant atoms in the channel decreases with scaled dimensions, the impact of the variation associated with the atoms increases. Figure 2 illustrates the decreasing average number of dopant atoms in the channel as a function of the technology node. Note the change from the 1μm technology node (with many thousands of dopant atoms in the channel) to the 32nm technology node (with less than 100 atoms in the channel). Figure 1: Random dopant fluctuations (RDF) are an important effect in sub-micron CMOS technologies RDF is assumed to be the major contributor to device mismatch of identical adjacent devices and is frequently represented by Stolk’s formulation (Equation 1) illustrating that matching improves with decreases in channel doping (N) and gate oxide thickness (Tox), and it degrades when device area decreases [12]. ) 1 ( 2 1