Investigation of Threshold Voltage Distribution Temperature Dependence in 3D NAND Flash

The impact of temperature on array Vth distribution was investigated in 3D NAND flash. Cell Vth distributions were obtained under different program and read temperature splits. After the page is programmed under high temperature, it is found that the high tail of Vth distribution exhibits a larger shift than the low tail, during read at different temperatures (85 °C and −25 °C). On the contrary, the low tail of Vth distribution shows a larger shift than the high tail during cross temperature read, after the page programmed under low temperature. The temperature coefficient (Tco) of cell Vth shows cell to cell variations, which can be categorized into two types. For type ①, the Tco is correlated with the selected cell Vth due to polysilicon channel. For type ②, the Tco is independent of the selected cell Vth. The corresponding impacts on Vth distribution are studied via array Monte Carlo simulation. Based on the simulation results, the above temperature dependent observations can be well modeled by the combination of both Tco variation type ① and ②. Furthermore, two optimization approaches are proposed to alleviate the Vth distribution broadening and are validated by experiments.

[1]  T. Tanzawa,et al.  A temperature compensation word-line voltage generator for multi-level cell NAND Flash memories , 2010, 2010 Proceedings of ESSCIRC.

[2]  M. Meyyappan,et al.  The temperature dependence of threshold voltage variations due to oblique single grain boundary in 3D NAND unit cells , 2014, 2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS).

[3]  Chih-Yuan Lu,et al.  A Monte Carlo simulation method to predict large-density NAND product memory window from small-array test element group (TEG) verified on a 3D NAND Flash test chip , 2016, 2016 IEEE Symposium on VLSI Technology.

[4]  Haibo Li Modeling of Threshold Voltage Distribution in NAND Flash Memory: A Monte Carlo Method , 2016, IEEE Transactions on Electron Devices.

[5]  G. M. Paolucci,et al.  Temperature activation of the string current and its variability in 3-D NAND flash arrays , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

[6]  Andrea L. Lacaita,et al.  Reviewing the Evolution of the NAND Flash Technology , 2017, Proceedings of the IEEE.

[7]  Xingqi Zou,et al.  A Novel Read Scheme for Read Disturbance Suppression in 3D NAND Flash Memory , 2017, IEEE Electron Device Letters.

[8]  Niccolò Righetti,et al.  2D vs 3D NAND technology: Reliability benchmark , 2017, 2017 IEEE International Integrated Reliability Workshop (IIRW).

[9]  Carmine Miccoli,et al.  Temperature Effects in NAND Flash Memories: A Comparison Between 2-D and 3-D Arrays , 2017, IEEE Electron Device Letters.

[10]  G. M. Paolucci,et al.  Characterization and Modeling of Temperature Effects in 3-D NAND Flash Arrays—Part I: Polysilicon-Induced Variability , 2018, IEEE Transactions on Electron Devices.

[11]  Xingqi Zou,et al.  A Novel Program Scheme for Program Disturbance Optimization in 3-D NAND Flash Memory , 2018, IEEE Electron Device Letters.

[12]  Kyungmin Kim,et al.  A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

[13]  Guoxing Chen,et al.  Investigation of Cycling-Induced Dummy Cell Disturbance in 3D NAND Flash Memory , 2018, IEEE Electron Device Letters.