Reconfigurable subthreshold CMOS perceptron

We present an idea for a new real-time reconfigurable perceptron, also called, a threshold element. The circuit example contain three inverters with shorted outputs. SPICE simulations for a 0.6 /spl mu/m CMOS implementation operating in the subthreshold region. are shown. The threshold voltages of the active devices, seen from driving nodes, may be dynamically changed by adjusting their substrate potentials. This enables a change of the threshold of the perceptron circuit in real-time. In terms of Boolean logic the functionality may be changed between 3-input NOR, CARRY' for the FULL-ADDER function and 3-input NAND, in real-time.

[1]  Valeriu Beiu,et al.  VLSI implementations of threshold logic-a comprehensive survey , 2003, IEEE Trans. Neural Networks.

[2]  Valeriu Beiu,et al.  Deeper Sparsely Nets can be Optimal , 1998, Neural Processing Letters.

[3]  Massoud Pedram,et al.  Low power design methodologies , 1996 .

[4]  Yngvar Berg,et al.  Programmable floating-gate MOS logic for low-power operation , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[5]  Yngvar Berg,et al.  Real-time reconfigurable linear threshold elements implemented in floating-gate CMOS , 2003, IEEE Trans. Neural Networks.

[6]  Kaushik Roy,et al.  Robust subthreshold logic for ultra-low power operation , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[7]  Snorre Aunet,et al.  Four-MOSFET Floating-Gate UV-Programmable Elements for Multifunction Binary Logic , 2001 .

[8]  Trond Ytterdal,et al.  Compact low-voltage self-calibrating digital floating-gate CMOS logic circuits , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[9]  Tadahiro Ohmi,et al.  An intelligent MOS transistor featuring gate-level weighted sum and threshold operations , 1991, International Electron Devices Meeting 1991 [Technical Digest].

[10]  T. Sakurai,et al.  Self-adjusting threshold-voltage scheme (SATS) for low-voltage high-speed operation , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[11]  Robert J. Francis,et al.  Ganged CMOS: trading standby power for speed , 1990 .

[12]  P.P. Gelsinger,et al.  Microprocessors for the new millennium: Challenges, opportunities, and new frontiers , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[13]  M. G. Johnson A symmetric CMOS NOR gate for high-speed applications , 1988 .

[14]  Andreas G. Andreou,et al.  Current-mode subthreshold MOS circuits for analog VLSI neural systems , 1991, IEEE Trans. Neural Networks.