Efficient BIST scheme for A/D converters

As SOC and complex systems usually include analogue IPs, it becomes more important to test analogue devices efficiently. The reason for this is that analogue testing for high quality requires substantial testing costs although the analogue portion in a whole chip or in a system is usually very small. In the paper, an efficient low-cost built-in self-test (BIST) scheme is developed for testing A/D converters. The key ideas are to use a triangular wave as a test input signal and to analyse the output response for functional testing. In order to perform functional testing, new fault models called successive value, oscillation and bit faults are proposed. Testing these faults guarantees the quality of A/D converters. For experimental results, a D-S A/D converter and a pipeline A/D converter are used. The results show that the new BIST scheme is very efficient in terms of fault coverage and hardware overhead. the presence of pre-existing DSP capabilities and the presence of both an A/D converter and a D/A converter. Another BIST approach uses pulse response sampling (4). This BIST uses pulse trains of varying duty ratio, generated from a digital linear feedback shift register (LFSR), as a test stimulus. The responses of the device under test (DUT) are sampled and compared with reference voltages to generate binary sequences that can be compressed to yield a signature for the anticipated responses. The BIST scheme using pulse response sampling has the advantage of a very small hardware overhead, but it takes a long time to test in high fault conditions. Finally, the BIST architecture, which is most widely known, is a histogram-based analogue BIST architecture (5-7). This method is based on statistical analysis of the A/D converter output code. In this approach, an analogue signal is applied to the A/D converter input and the number of times each code appears on the A/D converter output is recorded. These recorded samples are compared with theoretical values and then the BIST makes a decision whether the A/D converter is fault- free or faulty. To store both the measured and ideal histograms, the histogram test technique requires a large amount of hardware resources both in terms of memory and operative resources. In addition, a large number of samples and several successive periods of the signal are required to achieve satisfactory results. This paper investigates the viability of a new BIST approach. The input test signal waveform of A/D converters is a triangular wave obtained from an integrator. Then the output of the A/D converters is compared with the reference voltages, which are related to the three defined fault models used by the BIST. The proposed scheme is applicable to any A/D converter because it is related to functional testing. Comparing this new BIST with other BIST, this scheme does not need any DSP resources. Moreover, the proposed BIST has a small hardware overhead but achieves high fault coverage. Just three periods of input signal are required to achieve high fault coverage, so test time is reduced. 2 New test methodology