Semiconductor memory device capable of increasing input/output line number without increase in chip area

This semiconductor memory device disclosed is arranged between adjacent memory block of the memory block includes a plurality of sense amplifier blocks each having the open gate region and the first and second sense amplifier region. The open gate region of the sense amplifier block and the first and second sense amplifier regions are arranged in a matrix form of rows and columns. Open the gate regions of the sense amplifier block are arranged at least in two rows. Between the line (or word line), a gate region adjacent columns are arranged in a direction that either one of the first and second sense amplifier region is disposed.