Localization of Bugs in Processor Designs Using zamiaCAD Framework

This paper proposes an approach to automatic localization of design errors (bugs) in processor designs based on combining statistical analysis of dynamically covered VHDL code items and static slicing. The approach considers coverage of different VHDL code items including statements, branches and conditions during processor simulation which together contribute to accurate localization of bugs. The accuracy of analysis is further improved by applying a static slicing based filter calculated by means of reference graph generation using a through-signal-assignment search from the semantically resolved elaborated models of processor designs. The localization approach has been integrated to highly scalable zamiaCAD RTL design framework. The efficiency of the proposed approach is demonstrated by applying it to debugging of an industrial processor ROBSY designed for FPGA-based test systems. The experimental results evaluate the approach for a set of real documented bug cases and the original functional test.

[1]  Heinz-Dietrich Wuttke,et al.  Architecture of an Adaptive Test System Built on FPGAs , 2011, ARCS.

[2]  Roderick Bloem,et al.  Finding and fixing faults , 2005, J. Comput. Syst. Sci..

[3]  David W. Binkley,et al.  Program slicing , 2008, 2008 Frontiers of Software Maintenance.

[4]  Ibrahim N. Hajj,et al.  Design error diagnosis and correction via test vector simulation , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Heinz-Dietrich Wuttke,et al.  Automatic generation of an FPGA based embedded test system for printed circuit board testing , 2012, 2012 13th Latin American Test Workshop (LATW).

[6]  Jaan Raik,et al.  A scalable model based RTL framework zamiaCAD for static analysis , 2012, 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC).

[7]  Aaas News,et al.  Book Reviews , 1893, Buffalo Medical and Surgical Journal.

[8]  Mary Jean Harrold,et al.  Empirical evaluation of the tarantula automatic fault-localization technique , 2005, ASE.

[9]  Janusz W. Laski,et al.  Dynamic Program Slicing , 1988, Inf. Process. Lett..

[10]  Franz Wotawa,et al.  Debugging VHDL Designs: Introducing Multiple Models and First Empirical Results , 2004, Applied Intelligence.

[11]  Byoungju Choi,et al.  A family of code coverage-based heuristics for effective fault localization , 2010, J. Syst. Softw..

[12]  Michael I. Jordan,et al.  Scalable statistical bug isolation , 2005, PLDI '05.

[13]  Andreas Veneris,et al.  Design diagnosis using Boolean satisfiability , 2004 .

[14]  Roderick Bloem,et al.  Automated error localization and correction for imperative programs , 2011, 2011 Formal Methods in Computer-Aided Design (FMCAD).

[15]  Yu Qi,et al.  Bp Neural Network-Based Effective Fault Localization , 2009, Int. J. Softw. Eng. Knowl. Eng..

[16]  Masahiro Fujita,et al.  Program slicing for VHDL , 2002 .

[17]  Andreas Zeller,et al.  Locating causes of program failures , 2005, Proceedings. 27th International Conference on Software Engineering, 2005. ICSE 2005..

[18]  Raimund Ubar,et al.  High-level design error diagnosis using backtrace on decision diagrams , 2010, NORCHIP 2010.

[19]  Chao Liu,et al.  Statistical Debugging: A Hypothesis Testing-Based Approach , 2006, IEEE Transactions on Software Engineering.

[20]  Franz Wotawa,et al.  Automated source-level error localization in hardware designs , 2006, IEEE Design & Test of Computers.