Accurate modeling for CMOS inverter overshooting time in nanoscale paradigm
暂无分享,去创建一个
[1] Labros Bisdounis,et al. Analytical Modeling of Overshooting Effect in Sub-100 nm CMOS inverters , 2011, J. Circuits Syst. Comput..
[2] Kaushik Roy,et al. Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[3] A Contactless Method for Determining the Carrier Mobility Sum in Silicon Wafers , 2012, IEEE Journal of Photovoltaics.
[4] G. Iannaccone,et al. A Backscattering Model Incorporating the Effective Carrier Temperature in Nano-MOSFET , 2011, IEEE Electron Device Letters.
[5] Tahir Ghani. Innovations to extend CMOS nano-transistors to the limit , 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).
[6] R. J. Mears,et al. Simultaneous carrier transport enhancement and variability reduction in Si MOSFETs by insertion of partial monolayers of oxygen , 2012, 2012 IEEE Silicon Nanoelectronics Workshop (SNW).
[7] Mark S. Lundstrom. Elementary scattering theory of the Si MOSFET , 1997, IEEE Electron Device Letters.