Method of glitch reduction in DAC with weight redundancy

The appearance of glitches in digital-to-analog converters leads to significant limitations of conversion accuracy and speed, which is critical for DAC and limits their usage. This paper researches the possibility of using the redundant positional number system in order to reduce glitches in DAC. There had been described the usage pattern of number systems with fractional digit weights of bits as well as with the whole number weights of bits. Hereafter there had been suggested the algorithm for glitches reduction in the DAC generation mode of incessant analogue signal. There had also been estimated the efficiency of weight redundancy application with further presentation of the most efficient parameters of number systems. The paper describes a block diagram of a low-glitch DAC based on Fibonacci codes. The simulation results prove the feasibility of weight redundancy application and show a significant reduction of glitches in DAC in comparison with the classical binary system.